Intel CONTROLLERS 413808 - Manual (Page 437)

Intel ® 413808 and 413812 I/O Controllers in TPER Mode
October 2007 Developer’s Manual
Order Number: 317805-001US 437
Messaging Unit—Intel
®
413808 and 413812
4.7.28 MSI-X Message Control Register - MSI-X_MCR
MSI-X Capabilities bits adhere to the definitions in the PCI Local Bus Specification,
Revision 2.3. This register is a 16-bit read-only register which provides information on
the capabilities of the ATU function related to Message Signaled Interrupts.
Note: Refer to the Peripheral Registers Chapter for the default internal bus address. This
register is part of the configuration space of the Address Translation Unit that is setup
as an endpoint.
Table 293. MSI-X Message Control Register - MSI-X_MCR
Bit Default Description
15 0
2
MSI-X Enable: When set, the 4138xx is able to use MSI-X to request service.
14 0
2
Function Mask: When set, all the vectors in the MSI-X Table are globally masked, regardless of the
per-vector Mask Bit states in the Vector Control Register of the MSI-X Table entries.
13:11 000
2
Reserved
10:00
00000000000
2
or
00000000111
2
(See description
for default
value)
MSI-X Table Size: This field indicates the MSI-X Table size N. This field is encoded as N-1. Up to
eight messages can be generated. However, when the MSI-X Single Message Vector bit is set in the
“MU MSI-X Control Register X — MMCRx” on page 440 , only a single MSI-X message is generated. The
value of this register field is dependent on the setting of the MSI-X Single Message Vector bit.
MSI-X Single Message Bit Default Value
0 00000000111
2
1 00000000000
2
PCI
IOP
Attributes
Attributes
15 12 8 4 0
rw
rw
rw
rw
rv
rv
rv
rv
rv
rv
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
Attribute Legend:
RV = Reserved
PR = Preserved
RS = Read/Set
RW = Read/Write
RC = Read Clear
RO = Read Only
NA = Not Accessible
PCI Configuration Offset
B2 - B3H
Internal Bus Address Offset
0B2H