Intel CONTROLLERS 413808 - Manual (Page 522)

Intel
®
413808 and 413812—SRAM Memory Controller
Intel ® 413808 and 413812 I/O Controllers in TPER Mode
Developer’s Manual October 2007
522 Order Number: 317805-001US
8.3.3.3 ECC Checking
The ECC logic uses the following ECC read algorithm. This algorithm corrects the data
before it's driven onto the internal bus. The ECC algorithm for a read transaction is:
Read 32-bit data and 7-bit ECC
Compute the syndrome by passing the 32-bit data through the G-Matrix and XORing the
7-bit result with the 7-bit ECC
if the syndrome <> 0 {ECC Error}
Look up in H-matrix to determine error type
Register the address where the error occurred
if error is correctable {single bit}
if single-bit error correction is enabled
Correct data
Send corrected data to internal bus
if single bit error reporting is enabled
Interrupt core for software scrubbing
else {uncorrectable}
if the read cycle is not part of a RMW cycle {read}
Target-Abort the Internal Bus read transaction.
else {write requiring RMW}
Merge the new data portion with the read data from memory
Generate the new ECC with the G-matrix
Write new data and ECC
if multi-bit error reporting is enabled
Interrupt the core for uncorrectable error
When the SMCU reads the ECC from the memory subsystem, it is compared (XORed)
with an ECC result that the SMCU generates from the data read from the memory. The
resulting value of the XOR operation is called the syndrome. Table 346 shows how the
SMCU decodes the syndrome for SRAM read cycles.
Table 346. Syndrome Decoding
Error Type Symptom
None The syndrome is 0000 0000.
Single-Bit Use the H-Matrix in Figure 60 to determine which bit the SMCU will invert to fix the error.
Multi-Bit If the Syndrome does not match an 7-bit value in the H-matrix, the error is uncorrectable