Messaging unit—intel, Bit default description – Intel CONTROLLERS 413808 User Manual

Page 419

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Intel

413808 and 413812 I/O Controllers in TPER Mode

October 2007

Developer’s Manual

Order Number: 317805-001US

419

Messaging Unit—Intel

413808 and 413812

4.7.9

Inbound Reset Control and Status Register - IRCSR

The Inbound Reset Control and Status Register (IRCSR) provides the ability for the

Host processor to request a Selective Reset or a Coordinate Reset. A selective reset is

used to perform a soft reset. A selective reset is requested by the host processor

setting the Selective Reset bit of the IRCSR, which causes an Intel XScale

processor

interrupt.
A coordinated reset is used when supporting multiple PCI functions. In a multi-function

scenario, before the Host driver can issue a hardware reset via one of the PCI

functions, all the host drivers running must be quiesced. A coordinated reset is

requested by the host processor setting the Coordinated Reset bit in the IRCSR, which

causes an Intel XScale

processor interrupt. After all the host drivers have been

quiesced, the host driver that initiated the coordinated reset would request a hardware

reset of the 4138xx. When the host driver sets both the Selective Reset and

Coordinated Reset bits simultaneously, an internal bus reset is initiated.

Note:

An internal bus reset event that is caused by setting both the CR and SR bits of the

IRCSR is indicated in the Reset Cause and Status Register (RCSR). For example, after

an internal bus reset the cause of the internal bus reset can be identified by reading the

RCSR. Refer to the

Chapter 7.0, “System Controller (SC) and Internal Bus Bridge”

for

detailed descriptions of the RCSR register.

Table 274. Inbound Reset Control and Status Register - IRCSR

Bit

Default

Description

31:02

00000000H Reserved.

Coordinated Reset (CR) - This bit is valid when the 4138xx implements Multi-Function Reset protocol,

(MF=1, bit 1 in the ORCSR). A Host driver writes a one into this bit to request a Coordinated Reset.

Writing a 1 to the CR bit would generate an interrupt to the Intel XScale

processor. However, writing

1’s to the CR bit and the SR bit simultaneously would instead generate an internal bus reset. In a

Coordinated Reset (only CR bit set), each function is notified and acknowledges the internal bus reset

before it actually occurs. In an internal bus reset, the reset proceeds immediately without any

notification to the any of the other Hosts.

Selective Reset (SR) - The Host driver sets this bit in order to request a firmware state and structures

re-initialization. Setting this bit generates an interrupt to the Intel XScale

processor. However, writing

1’s to the CR bit and the SR bit simultaneously would instead generate an internal bus reset. Setting the

SR bit by itself does not generate an internal bus reset. Therefore, the Intel XScale

processor must be

operational for the reset to be processed. Setting this bit has no impact on any other functions on

4138xx.

PCI

IOP

Attributes

Attribute Legend:

RV = Reserved

PR = Preserved

RS = Read/Set

RW = Read/Write

RC = Read Clear

RO = Read Only

NA = Not Accessible

MU/PCI Base Address Offset

OIMR: 0038H

internal bus address offset

OIMR: 4038H

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