Intel CONTROLLERS 413808 - Manual (Page 663)

Intel ® 413808 and 413812 I/O Controllers in TPER Mode
October 2007 Developer’s Manual
Order Number: 317805-001US 663
UARTs—Intel ® 413808 and 413812
13.3.1 FIFO Interrupt Mode Operation
13.3.1.1 Receiver Interrupt
When the Receive FIFO and receiver interrupts are enabled (FCR[0]=1 and IER[0]=1),
receiver interrupts occur as follows:
• The Receive Data Available Interrupt is asserted when the FIFO has reached its
programmed trigger level. The interrupt is cleared when the FIFO drops below the
programmed trigger level.
• The IIR Receive Data Available indication also occurs when the FIFO trigger level is
reached, and like the interrupt, the bits are cleared when the FIFO drops below the
trigger level.
• The Data Ready bit (DR in LSR register) is set to 1 as soon as a character is
transferred from the shift register to the Receive FIFO. This bit is reset to 0 when
the FIFO is empty.
13.3.1.2 Transmit Interrupt
When the transmitter FIFO and transmitter interrupt are enabled (FCR[0]=1,
IER[1]=1), transmit interrupts occur as follows:
• When the Flow Control Register Transmitter Interrupt Level (TIL) bit (FCR[3]) is
clear (0), The Transmit Data Request interrupt occurs when the transmit FIFO is
half empty or more than half empty. The interrupt is cleared when the data level
exceeds the half-empty mark. The interrupt is cleared as soon as the Transmit
Holding Register is written or the IIR is read. 1 to 32 characters may be written to
the transmit FIFO while servicing the interrupt when TIL=0.
• When the Flow Control Register Transmitter Interrupt Level (TIL) bit is set (1), The
Transmit Data Request Interrupt occurs when the Transmit FIFO is empty. The
interrupt is cleared as soon as the Transmit Holding Register is written or the IIR is
read. 1 to 64 characters may be written to the Transmit FIFO while servicing the
interrupt when TIL = 1.
Users could cause the UART Transmit FIFO to overflow when too many characters are
written. FIFO underflow does not cause an error as the UART waits for the Transmit
FIFO to be serviced.