Intel CONTROLLERS 413808 - Manual (Page 791)

Intel ® 413808 and 413812 I/O Controllers in TPER Mode
October 2007 Developer’s Manual
Order Number: 317805-001US 791
Test Logic Unit and Testability—Intel ® 413808 and 413812
18.2.3.2 Instructions
Each of the TAP controller instruction sets is composed of both public and private
instructions. Public instructions are intended for use by purchasers of the part. Since
the instruction set for each TAP controllers is independent of one another, each is listed
separately below
Table 519. TLU TAP Controller Instruction Set
Instruction Opcode Public/Private Description
EXTEST 0000000
2
Public
Intended for supporting the boundary-scan feature for testing
device interconnects at the board/system level, the EXTEST
instruction connects only the boundary-scan register between TDI
and TDO in the Shift-DR state. When EXTEST is selected, all output
signal pin values are driven by values shifted into the
boundary-scan register and may change only on the falling-edge of
TCK in the Update_DR state.
Also, when extest is selected, all system input pin states must be
loaded into the boundary-scan register on the rising-edge of TCK in
the Capture_DR state.
Note: Data would typically be loaded onto the latched parallel
outputs of boundary-scan shift registers using the
SAMPLE/PRELOAD instruction prior to selection of the
EXTEST instruction.
SAMPLE/
PRELOAD
0000001
2
Public
SAMPLE/PRELOAD performs two functions:
• When the TAP controller is in the Capture-DR state, the sample
instruction occurs on the rising edge of TCK and provides a
snapshot of the component’s normal operation without interfering
with that normal operation. The instruction causes Boundary-Scan
register cells associated with outputs to sample the value being
driven by or to the processor.
• When the TAP controller is in the Update-DR state, the preload
instruction occurs on the falling edge of TCK . This instruction
causes the transfer of data held in the boundary-scan cells to the
slave register cells. Typically the slave latched data is then applied
to the system outputs by means of the extest instruction.
HIGHZ 0101110
2
Public
HIGHZ puts all output pins into a tri-state mode. When this
instruction is active, the bypass register is connected between TDI
and TDO .
CLAMP 0101111
2
Public
Once the clamp instruction is loaded into the TAP controller
instruction register, the output pins are driven by the parallel output
of the boundary-scan chain. The bypass register is selected as the
serial path between TDI and TDO when the TAP controller passes
through the Shift-DR state.
IDCODE 1111110
2
Public
IDCODE is used in conjunction with the device identification
register. When selected, IDCODE parallel-loads the hard-wired
identification code (32 bits) into the identification register on the
rising edge of TCK following entry into the Capture-DR state. The
instruction selects only the identification register for connection
between TDI and TDO in the Shift-DR state for serial access.
Note: The device identification register is not altered by data
being shifted in on TDI .
BYPASS 1111111
2
Public
BYPASS selects the bypass register between TDI and TDO while in
Shift-DR state, effectively bypassing the processor’s test logic. 0 is
captured in the Capture-DR state. While this instruction is in effect,
all other test data registers have no effect on the operation of the
system.