Intel CONTROLLERS 413808 - Manual (Page 233)

Intel ® 413808 and 413812 I/O Controllers in TPER Mode
October 2007 Developer’s Manual
Order Number: 317805-001US 233
Address Translation Unit (PCI Express)—Intel
®
413808 and 413812
3.2 PCI Express Link Characteristics
The PCI Express* port supports x8, x4, x2, and x1 operation. Lane reversal and
polarity inversion automatically occur in an attempt to successfully train the link.
The PCI Express port is configured to ease adapter card implementations. The lane
number and lane polarity should enable straight routing between the component and
the PCI Express card edge connector. The lane reversal feature can be utilized to
simplify applications where this component is connected to the upstream device in a
planar fashion. For example integrating the device on a motherboard with direct
connection to the I/O Hub.
Supported Lane Reversal Modes
x8
7:0, 0:7
x4 3:0, 0:3
x2 1:0, 0:1
x1 0, 7
Port bifurcation is not supported. This component supports a single x8 PCI Express port
and can not be split into multiple x4 ports.
The PCI Express interface supports a maximum payload size of 512 Bytes and returns
completions with minimum of 128 byte payloads.