Intel CONTROLLERS 413808 - Manual (Page 21)

Intel ® 413808 and 413812 I/O Controllers in TPER Mode
October 2007 Developer’s Manual
Order Number: 317805-001US 21
Contents—Intel
®
413808 and 413812
Figures
1 TPER Architecture Overview ...................................................................................... 37
2 Intel
®
413808 and 413812 I/O Controllers in TPER Mode Functional Block Diagram .......... 43
3 ATU Block Diagram .................................................................................................. 51
4 ATU Queue Architecture Block Diagram....................................................................... 52
5 Inbound Address Detection........................................................................................ 57
6 Inbound Translation Example..................................................................................... 58
7 4 Gbyte Section 0 of the Internal Bus Memory Map....................................................... 68
8 Outbound Address Translation Windows...................................................................... 69
9 Inbound Byte Swapping for 32-bit PCI ........................................................................ 78
10 Inbound Byte Swapping for 64-bit PCI ........................................................................ 78
11 Outbound Byte Swapping for Transaction with Byte Count of 1....................................... 79
12 Outbound Byte Swapping for Transaction with Byte Count of 2....................................... 79
13 Outbound Byte Swapping for Transaction with Byte Count of 3 or Larger ......................... 79
14 PCI-X Initialization Pattern Setting / Drive................................................................. 137
15 ATU Interface Configuration Header Format............................................................... 139
16 ATU Interface Extended Configuration Header Format (Power Management) .................. 140
17 ATU Interface Extended Configuration Header Format (MSI-X Capability) ...................... 140
18 ATU Interface Extended Configuration Header Format (MSI Capability).......................... 141
19 ATU Interface Extended Configuration Header Format (PCI-X Capability Type 1)............. 141
20 ATU Extended Configuration Header Format (Compact PCI Hot-Swap Capability) ............ 142
21 ATU Interface Extended Configuration Header Format (VPD Capability) ......................... 142
22 ATU Block Diagram ................................................................................................ 231
23 ATU Queue Architecture Block Diagram..................................................................... 232
24 Inbound Address Detection...................................................................................... 238
25 Inbound Translation Example................................................................................... 239
26 4 Gbyte Section 0 of the Internal Bus Memory Map..................................................... 247
27 Outbound Address Translation Windows.................................................................... 249
28 Inbound Byte Swapping .......................................................................................... 255
29 Outbound Byte Swapping for Transaction with Byte Count of 1..................................... 256
30 Outbound Byte Swapping for Transactions with Byte Count of 2 ................................... 256
31 Outbound Byte Swapping Transaction with Byte Count of 3 or Larger............................ 256
32 ATU Interface Configuration Header Format............................................................... 289
33 ATU Interface Extended Configuration Header Format (Power Management) .................. 290
34 ATU Interface Extended Configuration Header Format (MSI-X Capability) ...................... 290
35 ATU Interface Extended Configuration Header Format (MSI Capability).......................... 291
36 ATU Interface Extended Configuration Header Format (PCI Express Capability)............... 291
37 ATU Interface Extended Configuration Header Format (VPD Capability) ......................... 291
38 PCI Express Vendor_Defined Message Header............................................................ 384
39 PCI Memory Map.................................................................................................... 400
40 Internal Bus Memory Map ....................................................................................... 401
41 MSI-X Table and PBA Address Mapping Layout relative to the Host Interface.................. 408
42 MSI-X Table and PBA Address Mapping Layout relative to the Internal Bus..................... 409
43 SGPIO Bus Overview .............................................................................................. 459
44 SGPIO Repeating Bit Stream.................................................................................... 460
45 SLoad Signal ......................................................................................................... 460
46 SDataOut Signal .................................................................................................... 461
47 SDataIn Signal ...................................................................................................... 461
48 Clock Structure...................................................................................................... 462
49 SGPIO Output OD0 Signal ....................................................................................... 463
50 SGPIO Output OD1 Signal ....................................................................................... 464
51 SGPIO Output OD2 Signal ....................................................................................... 464
52 Output Signal Routing............................................................................................. 469
53 Intel
®
413808 and 413812 I/O Controllers in TPER Mode SGPIO Unit 0 Pin Mapping ....... 472