Intel CONTROLLERS 413808 - Manual (Page 494)

Intel
®
413808 and 413812—System Controller (SC) and Internal Bus Bridge
Intel ® 413808 and 413812 I/O Controllers in TPER Mode
Developer’s Manual October 2007
494 Order Number: 317805-001US
7.3.6 Parity Support
The bridge supports parity as required by the south internal bus. The south internal bus
supports both byte-wise address and data parity. Therefore, as a initiator the bridge is
responsible to drive byte-wise parity on the south internal bus on both the 36-bit
address bus and the 128-bit data bus. Also when completing read requests for south
internal bus initiators, the bridge drives data parity. The south internal bus supports
even parity. Note that the north internal bus does not support any parity. The bridge
also supports byte-wise parity on the internal data buffers.
7.3.6.1 Address Parity Generation
Only the bridge south interface generates byte-wise address parity on address it
initiates on the south internal bus.
7.3.6.2 Address Parity Checking
Only the south interface of the bridge verifies address parity when claiming south
internal bus write transactions.
7.3.6.3 Data Parity on Outbound Transactions
For an outbound transaction (transaction flowing from the north internal bus to the
south internal bus as either a read completion or write request), the bridge generates
data parity as the data enters the north bridge interface. The data and its parity are
stored in the internal data buffers. When the transaction is initiated on the south
internal bus, the bridge simply drives the data along with the parity as stored in the
data buffers. For example, the bridge does not generate parity. The receiver of the data
on the south internal bus verifies the data parity.
7.3.6.4 Data Parity on Inbound Transactions
For an inbound transaction (transaction flowing from the south internal bus to the north
internal bus as either a read completion or a write request), the bridge simply writes
the data along with the received data parity to the internal data buffers. The bridge
then checks the data parity while forwarding the transaction to the north internal bus.
When the bridge detects a parity error on a write transaction, the bridge logs the error
and also forwards the transaction on the north internal bus. When the bridge detects a
parity error on a read completion, the bridge logs the error and assert DABORT instead
of completing the transaction on the north internal bus. Refer to the following error
logging registers: “Bridge Error Control and Status Register — BECSR” , “Bridge Error
Address Register — BERAR” and the “Bridge Error Upper Address Register — BERUAR”