Intel CONTROLLERS 413808 - Manual (Page 96)

Intel
®
413808 and 413812—Address Translation Unit (PCI-X)
Intel ® 413808 and 413812 I/O Controllers in TPER Mode
Developer’s Manual October 2007
96 Order Number: 317805-001US
2.7.2 Correctable Address and Correctable Attribute Errors on the PCI
Interface
In PCI-X Mode 2 (when single-bit correction is enabled), the ATUs must detect and
report correctable address and attribute (PCI-X mode only) errors for transactions on
the PCI bus. When a correctable address or attribute error occurs on the PCI interface
of the 4138xx, the ATU performs the following actions based on the constraints
specified:
• The error is corrected and the ATU completes the transaction on the PCI bus as
when no error had occurred. Then, the transaction is forwarded to the internal bus
normally.
• Update the “ECC Control and Status Register - ECCCSR” on page 195 , the “ECC
First Address Register - ECCFAR” on page 198 , the “ECC Second Address Register -
ECCSAR” on page 199 , and the “ECC Attribute Register - ECCAR” on page 200 for
the transaction.
— When the ATU Detected Correctable Error Interrupt Mask bit in the ATUIMR is
clear, set the Detected Correctable Error bit in the ATUISR. When set, no
action.
Note: The ECCCSR provides information on the transaction phase in which the correctable
error occurred.