Intel CONTROLLERS 413808 - Manual (Page 733)

Intel ® 413808 and 413812 I/O Controllers in TPER Mode
October 2007 Developer’s Manual
Order Number: 317805-001US 733
PMON Unit—Intel ® 413808 and 413812
Example 7 has been simplified by using 12 clocks as the sampling period. In a real
system the sampling would more likely be something like 1 ms. There is a certain
amount of overhead associated with writing and reading to any PMON registers. The
more frequent the interaction between the PMON counters and any software, the
larger the margin of error that is injected into the final results.
The sampling period can be controlled by a CPU counter or another
PMON counter
periodically interrupting the system and allowing the software to read data registers or
do whatever else may be desired.
Example 7. Simple Counting
This example demonstrates how to measure the number of times event A occurs during
12 clocks.
An alternative way to represent the data in the preceding table is as follow:
Write Event Register 0 (Increment = Event A)
Start Counter 0 immediately
Repeat every 12 clocks
Sample & Restart Counter 0 (Threshold Condition Code is NA)
Read Data Register 0
End Repeat
Table 481. Simple Time Based Counting of Events Example
Opcode Target Counter Increment Event Decrement Event Trigger Event
Write Event Register 0 Event A None (000h)
Start 0 Immed (000h)
* Sample & Restart 0 Immed (000h)
Read Data Register 0
-- Wait 12 clocks before returning to * --
Figure 110. Block Diagram and Waveforms of Time Based Sampling Example
B6300-01