Intel CONTROLLERS 413808 - Manual (Page 20)

Intel
®
413808 and 413812—Contents
Intel ® 413808 and 413812 I/O Controllers in TPER Mode
Developer’s Manual October 2007
20 Order Number: 317805-001US
18.2.2.15Exit2-IR State.........................................................................789
18.2.2.16Update-IR State......................................................................789
18.2.3 TAP Controller Registers ........................................................................790
18.2.3.1 Instruction Register.................................................................790
18.2.3.2 Instructions............................................................................791
18.2.3.3 Boundary-Scan Register...........................................................792
18.2.3.4 Bypass Register ......................................................................792
18.2.3.5 Device Identification Register....................................................792
18.3 Definition of Terms ..........................................................................................793
19.0 Peripheral Registers ..................................................................................................794
19.1 Overview........................................................................................................794
19.2 Accessing Peripheral Memory-Mapped Registers...................................................795
19.3 Accessing Peripheral Registers Using the Core Coprocessor Register Interface..........795
19.4 Architecturally Reserved Memory Space..............................................................795
19.5 Default Memory Space Setup ............................................................................796
19.6 Peripheral Memory-Mapped Register Address Space .............................................798
19.6.1 Internal Units.......................................................................................801
19.6.1.1 Peripheral Bus Interface Unit ....................................................801
19.6.1.2 System Controller ...................................................................802
19.6.1.3 Internal Bus Bridge..................................................................802
19.6.1.4 I/O Pad Control.......................................................................803
19.6.1.5 UART 0-1 ...............................................................................804
19.6.1.6 GPIO .....................................................................................805
19.6.1.7 I
2
C Bus Interface Unit 0-2 ........................................................805
19.6.1.8 Messaging Unit .......................................................................806
19.6.1.9 PMON Unit ............................................................................808
19.6.2 Host Interface Units ..............................................................................809
19.6.2.1 Address Translation Unit (PCI-X) ...............................................810
19.6.2.2 Address Translation Unit (PCI-E) ...............................................814
19.7 PCI Configuration Space ...................................................................................819
19.8 Coprocessor Register Space ..............................................................................819