Intel CONTROLLERS 413808 - Manual (Page 125)

Intel ® 413808 and 413812 I/O Controllers in TPER Mode
October 2007 Developer’s Manual
Order Number: 317805-001US 125
Address Translation Unit (PCI-X)—Intel
®
413808 and 413812
2.8 Message-Signaled Interrupts
The Messaging Unit is responsible for the generation of all of the Outbound Interrupts
from the 4138xx. These interrupts can be delivered to the Host Processor via the
P_INTA# output pin or the Message Signaled Interrupt (MSI) mechanism.
When a host processor enables Message-Signaled Interrupts (MSI) on the 4138xx, an
outbound interrupt is signaled to the host via a PCI write instead of the assertion of the
P_INTA# output pin.
In support of MSI, the 4138xx implements the MSI capability structure. The capability
structure includes the Section 4.7.20, “MSI Capability Identifier Register - Cap_ID” on
page 429 , the Section 4.7.21, “MSI Next Item Pointer Register - MSI_Next_Ptr” on
page 430 , the Section 4.7.23, “Message Address Register - Message_Address” on
page 432 , the Section 4.7.24, “Message Upper Address Register -
Message_Upper_Address” on page 433 and the Section 4.7.25, “Message Data
Register- Message_Data” on page 434 .
The Message Unit generates MSIs by writing to the MSI port via the internal bus. The
ATU generates a write transaction whenever the Message Unit writes to the MSI port,
using the address specified in the Section 4.7.23, “Message Address Register -
Message_Address” on page 432 , the Section 4.7.24, “Message Upper Address Register
- Message_Upper_Address” on page 433 and the Section 4.7.25, “Message Data
Register- Message_Data” on page 434 .