Intel CONTROLLERS 413808 - Manual (Page 563)

Intel ® 413808 and 413812 I/O Controllers in TPER Mode
October 2007 Developer’s Manual
Order Number: 317805-001US 563
Peripheral Bus Interface Unit—Intel
®
413808 and 413812
9.3.10 External Strap Status Register 0 — ESSTSR0
The External Strap Status Register 0 provides software a way to read the states of the
current settings of the straps. Refer to the Clock and Reset Chapter for external strap
descriptions.
Table 373. External Strap Status Register 0 — ESSTS0
Bit Default
a
a. Default values are product and feature dependent. See bit descriptions for default values.
Description
31:17 0000H Reserved.
16 x
2
CLK_SRC_PCIE#
15 x
2
INTERFACE_SEL_PCIX#
14 x
2
CONTROLLER_ONLY#
13 x
2
LK_DN_RST_BYPASS#
12 x
2
PCIX_PULLUP#
11:10 xx
2
Reserved.
09:07 xxx
2
DEFSEL[2:0]
06 x
2
BOOT_WIDTH_8#.
Note: This bit reflects the inverted value of the BOOT_WIDTH_8# strap.
05:04 xx
2
MEM_FREQ[1:0]
03:00 xxxx
2
SMBus Address Straps:
Register Bit SMBus Address Bit
0 SMB_A1
1 SMB_A2
2 SMB_A3
3 SMB_A5
PCI
IOP
Attributes
Attributes
28 24 20 16 12 8 4 0 31
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
ro
na
ro
na
ro
na
ro
na
ro
na
rv
na
rv
na
ro
na
ro
na
ro
na
ro
na
ro
na
ro
na
ro
na
ro
na
ro
na
ro
na
Attribute Legend:
RV = Reserved
PR = Preserved
RS = Read/Set
RW = Read/Write
RC = Read Clear
RO = Read Only
NA = Not Accessible
Intel XScale ® processor Local Bus Address offset
+2188H