Intel CONTROLLERS 413808 - Manual (Page 503)

Intel ® 413808 and 413812 I/O Controllers in TPER Mode
October 2007 Developer’s Manual
Order Number: 317805-001US 503
System Controller (SC) and Internal Bus Bridge—Intel
®
413808 and 413812
7.5.4 Peripheral Memory-Mapped Register Base Address Register —
PMMRBAR
This is a 32-bit register that contains the Base or starting address of the Peripheral
Memory-Mapped Register space (PMMR). The PMMR space is aligned on a 512-KByte
boundary. The PMMRBAR can be used to relocate the PMMR block to any 512-KByte
space of the 64 GBytes address space. Bits [31:15] of this register represent bits
[35:19] of the 36-bit internal bus address. The PMMR block default starting address
after reset is 0 FFD8 0000H.
Table 337. Peripheral Memory-Mapped Register Base Address Register — PMMRBAR
Bit Default Description
31:15 0000 1111 1111
1101 1
2
PMMR Base Address : These bits define the starting address of the PMMR block. The PMMR block is
aligned on a 512-KByte boundary. These bits represent bits [35:19] of the 36-bit internal bus
address.
Note: This value cannot be changed or the Transport Firmware does not execute.
14:00
000 0000 0000
0000
2
Reserved.
PCI
IOP
Attributes
Attributes
28 24 20 16 12 8 4 0 31
rw
na
rw
na
rw
na
rw
na
rw
na
rw
na
rw
na
rw
na
rw
na
rw
na
rw
na
rw
na
rw
na
rw
na
rw
na
rw
na
rw
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
Attribute Legend:
RV = Reserved
PR = Preserved
RS = Read/Set
RW = Read/Write
RC = Read Clear
RO = Read Only
NA = Not Accessible
Intel XScale ® processor Local Bus Address
F FFFF FFFCH South XBG