4 byte parity checking and generation, Port interface sram controller – Intel CONTROLLERS 413808 User Manual

Page 528

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Intel

®

413808 and 413812—SRAM Memory Controller

Intel

®

413808 and 413812 I/O Controllers in TPER Mode

Developer’s Manual

October 2007

528

Order Number: 317805-001US

8.3.4

Byte Parity Checking and Generation

All the direct memory ports of the SMCU supports byte-wise parity on the data bus.
For write requests made to an SMCU port, the direct memory port interface performs

the following tasks when receiving data:

• checks for data parity on the incoming data (parity error is logged if detected)

• generates ECC on the data

For the memory ports that are connected to the south internal bus, the write data

parity is received from the south internal bus as driven by the initiator of the data on

the south internal bus. For example, south internal bus initiators generate data parity.

Since the north internal bus does not support parity, data parity is generated by the

north internal bus port as the data enters the port and before it is written to the data

queue.
For read requests made to an SMCU port, the direct memory port interface performs

the following tasks before delivering data:

• checks for ECC on the data read from memory

• generates data parity on the data before delivering it on the port

For the memory ports that are connected to the south internal bus, the read data parity

that are generated by the SMCU are directly driven onto the south internal bus to the

requester. The data parity is then verified by the requester. Since the north internal bus

does not support parity, the read data parity that are generated by the SMCU are

verified by the north internal bus port when the data is read out of the data queue and

before being delivered onto the north internal bus. If the north internal bus port detects

a parity error while reading the data out of the data queue, the north internal bus port

will return a target abort.

Figure 61. Logical Data Access Paths with Parity Protection

Direct Memory

Data_in

Data_in Parity

Data_out Parity

Data_out

Port Interface

SRAM Controller

B6360-01

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