Intel CONTROLLERS 413808 - Manual (Page 667)

Intel ® 413808 and 413812 I/O Controllers in TPER Mode
October 2007 Developer’s Manual
Order Number: 317805-001US 667
UARTs—Intel ® 413808 and 413812
13.3.6 Manual Baud Rate Selection
Each UART contains a programmable Baud Rate Generator that is capable of taking the
fixed input clock of 33.334 MHz and dividing it by any divisor from 1 to (2
16
–1). The
baud-rate generator output frequency is 16 times the baud rate. Two 8-bit registers
store the divisor in a 16-bit binary format. These Divisor Registers must be loaded
during initialization to ensure proper operation. When both Divisor Latches are loaded
with 0, the 16X output clock is stopped. Access to the Divisor latch can be done with a
word write. Equation 17 or Table 443 are used by the programmer to select the Divisor
Latch value for the desired baud rate.