Intel CONTROLLERS 413808 - Manual (Page 700)

Intel ® 413808 and 413812—I 2 C Bus Interface Units
Intel ® 413808 and 413812 I/O Controllers in TPER Mode
Developer’s Manual October 2007
700 Order Number: 317805-001US
14.3.3 Arbitration
Arbitration on the I
2
C bus is required due to the multi-master capabilities of the I
2
C
bus. Arbitration is used when two or more masters simultaneously generate a START
condition within the minimum I
2
C hold time of the START condition.
Arbitration can continue for a long period. When the address bit and the R/W# are the
same, the arbitration moves to the data. Due to the wired-AND nature of the I
2
C bus,
no data is lost when both (or all) masters are outputting the same bus states. When
the address, the R/W# bit, or the data are different, the master which outputted the
high state (master’s data is different from SDA ) loses arbitration and shut its data
drivers off. When losing arbitration, the I
2
C Bus Interface Unit shuts off the SDA or SCL
drivers for the remainder of the byte transfer, set the Arbitration Loss Detected bit,
then return to idle (Slave-Receive) mode.
14.3.3.1 SCL Arbitration
Each master on the I
2
C bus generates its own clock on the SCL line for data transfers.
With masters generating their own clocks, clocks with different frequencies may be
connected to the SCL line. Since data is valid when the clock is in the high period, a
defined clock synchronization procedure is needed during bit-by-bit arbitration.
Clock synchronization is accomplished by using the wired-AND connection of the I
2
C
interfaces to the SCL line. When a master’s clock transitions from high to low, this
causes the master to hold down the SCL line for its associated period (see Figure 97 ).
The low to high transition of the clock may not change when another master has not
completed its period. Therefore, the master with the longest low period holds down the
SCL line. Masters with shorter periods are held in a high wait-state during this time.
Once the master with the longest period completes, the SCL line transitions to the high
state, masters with the shorter periods can continue the data cycle.
Figure 97. Clock Synchronization During the Arbitration Procedure
CLK1
SCL
Wait
State
Start Counting
High Period
CLK1
The first master to complete its
high period pulls the SCL line low.
The master with the longest
clock period holds the SCL
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