Intel CONTROLLERS 413808 - Manual (Page 567)

Intel ® 413808 and 413812 I/O Controllers in TPER Mode
October 2007 Developer’s Manual
Order Number: 317805-001US 567
Interrupt Controller Unit—Intel
®
413808 and 413812
10.3 The Intel XScale
®
Processor Exceptions Architecture
The Intel XScale
®
processor supports five types of exceptions
16
, and a privileged
processing mode for each type.
• IRQ and FIQ internal interrupt exceptions (normal and fast interrupts, respectively)
• memory aborts (used to implement memory protection or virtual memory)
• attempted execution of an undefined instruction
• software interrupts (SWIs) (used to make a call to an Operating System)
When an exception occurs, some of the standard registers are replaced with registers
specific to the exception mode. All exceptions have replacement (or banked) registers
for R14 and R13, and one interrupt mode has more registers for fast interrupt
processing.
After an exception, R14 holds the return address for exception processing, which is
used both to return after the exception is processed and to address the instruction that
caused the exception.
R13 is banked across exception modes to provide each exception handler with a private
stack pointer (SP). The fast interrupt mode also banks R8 to R12, so that interrupt
processing can begin without the need to save or restore these registers. There is a
seventh processing mode, System Mode, that does not have any banked registers (it
uses the User mode registers), which is used to run normal (non-exception) tasks that
require a privileged processor mode.
10.3.1 CPSR and SPSR
All other processor state is held in status registers. The current operating processor
status is in the Current Program Status Register or CPSR. The CPSR holds:
• Four condition code flags (Negative, Zero, Carry and Overflow)
• Two interrupt disable bits (one for each type of interrupt)
• Five bits which encode the current processor mode
All five exception modes also have a Saved Program Status Register (SPSR) which
holds the CPSR of the task immediately before the exception occurred. Both the CPSR
and SPSR are accessed with special instructions.
10.3.2 The Exception Process
Note: Refer to the System/Software Architecture Specification for details on the exception
process for the 4138xx in TPER mode during the common boot phase.
When an exception occurs, the Intel XScale
®
processor halts execution after the
current instruction and begins execution at a fixed address in low memory, known as
the exception vectors. There is a separate vector location for each exception (and two
for memory aborts to distinguish between data and instruction accesses).
An operating system installs a handler on every exception at initialization. Privileged
operating system tasks normally run in System mode to allow exceptions to occur
within the operating system without state loss (exceptions overwrite their R14 when an
exception occurs, and System mode is the only privileged mode that cannot be entered
by an exception).
16.Exception Description from the ARM Architecture Reference Manual, p. 1-3, Copyright Advanced
RISC Machines Ltd. (ARM) 1996