Intel CONTROLLERS 413808 - Manual (Page 61)

Intel ® 413808 and 413812 I/O Controllers in TPER Mode
October 2007 Developer’s Manual
Order Number: 317805-001US 61
Address Translation Unit (PCI-X)—Intel
®
413808 and 413812
2.2.1.3 Inbound Read Transaction
An inbound read transaction is initiated by a PCI initiator and is targeted at either
4138xx local memory or a 4138xx memory-mapped register space. The read
transaction is propagated through the inbound transaction queue (ITQ) and read data
is returned through the inbound read queue (IRQ).
When operating in the conventional PCI mode, all inbound read transactions are
processed as delayed read transactions. When operating in the PCI-X mode, all inbound
read transactions are processed as split transactions. The ATUs PCI interface claims the
read transaction and forwards the read request through to the internal bus and returns
the read data to the PCI bus. Data flow for an inbound read transaction on the PCI bus
is summarized in the following statements:
• The ATU claims the PCI read transaction when the PCI address is within the
inbound translation window defined by ATU Inbound Base Address Register (and
Inbound Upper Base Address Register during DACs) and Inbound Limit Register.
• When operating in the conventional PCI mode, when the ITQ is currently holding
transaction information from a previous delayed read, the current transaction
information is compared to the previous transaction information (based on the
setting of the DRC Alias bit in Section 2.14.40, “ATU Configuration Register -
ATUCR” on page 177 ). When there is a match and the data is in the IRQ, return the
data to the master on the PCI bus. When there is a match and the data is not
available, a Retry is signaled with no other action taken. When there is not a match
and when the ITQ has less than eight entries, capture the transaction information,
signal a Retry and initiate a delayed transaction. When there is not a match and
when the ITQ is full, then signal a Retry with no other action taken.
— When an uncorrectable address error is detected, the uncorrectable address
response defined in Section 2.7 is used.
• When operating in the conventional PCI mode, once read data is driven onto the
PCI bus from the IRQ, it continues until one of the following is true:
— The initiator completes the PCI transaction. When there is data left unread in
the IRQ, the data is flushed.
— An internal bus Target Abort was detected. In this case, the Q-word associated
with the Target Abort is never entered into the IRQ, and therefore is never
returned.
— Target Abort or a Disconnect with Data is returned in response to the Internal
Bus Error.
— The IRQ becomes empty. In this case, the PCI interface signals a Disconnect
with data to the initiator on the last data word available.
• When operating in the PCI-X mode, when ITQ is not full, the PCI address, attribute
and command are latched into the available ITQ and a Split Response Termination
is signalled to the initiator.
• When operating in the PCI-X mode, when the transaction does not cross a 1024
byte aligned boundary, then the ATU waits until it receives the full byte count from
the internal bus target before returning read data by generating the split
completion transaction on the PCI-X bus. When the read requested crosses at least
one 1024 byte boundary, then ATU completes the transfer by returning data in1024
byte aligned chunks.