Intel CONTROLLERS 413808 - Manual (Page 683)

Intel ® 413808 and 413812 I/O Controllers in TPER Mode
October 2007 Developer’s Manual
Order Number: 317805-001US 683
UARTs—Intel ® 413808 and 413812
Table 456. UART x Modem Status Register
This register provides the current state of the control lines from the modem or data set
(or a peripheral device emulating a modem). In addition to this current state
information, the Modem Status register also provides change information. The change
bit is set to a logic 1 when the control input from the Modem changes state. The change
bit is reset to a logic 0 when the processor reads the Modem Status register.
Note: When the change bit (bit 0) is set to logic 1, a Modem Status interrupt is generated
when bit 3 of the Interrupt Enable Register is set.
Table 457. UART x Modem Status Register - (UxMSR)
Bit Default Description
31:5 000 0000h Reserved
4 0
2
Clear to Send (CTS): This bit is the complement of the Clear to Send (CTS#) input.
This bit is equivalent to bit RTS of the Modem Control register when LOOP in the
MCR is set to 1.
0 = CTS# pin is 1
1 = CTS# pin is 0
3:1 000
2
Reserved
0 0
2
Delta Clear To Send (DCTS):
0 = No change in CTS# pin since last read of MSR
1 = CTS# pin has changed state
PC
I
IO
P
A
tt
ri
bu
te
s
A
tt
ri
bu
te
s
28 24 20 16 12 8 4 0 31
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
ro
na
rv
na
rv
na
rv
na
ro
na
Unit #
01
Intel XScale ® Core internal bus address
+2318H (DLAB=x)
+2358H (DLAB=x)
Attribute Legend:
RV = Reserved
PR = Preserved
RS = Read/Set
RW = Read/Write
RC = Read Clear
RO = Read Only
NA = Not Accessible