Intel CONTROLLERS 413808 - Manual (Page 470)

Intel
®
413808 and 413812—SGPIO Unit
Intel ® 413808 and 413812 I/O Controllers in TPER Mode
Developer’s Manual October 2007
470 Order Number: 317805-001US
Example 4. SGPIO Unit 0 is in Direct LED mode supporting Drives [4,6] and SGPIO Unit 1
is in SGPIO Mode supporting Drives[1,3,5,7]
In this example, SGPIO unit 0 is set up in Direct LED mode supporting Drive 4 and
Drive 6. Bit[0] in Table 321, “SGPIO Interface Control Register x - SGICRx” on
page 475 must be cleared for SGPIO unit 0, as this sets up the external pins for Direct
LED mode. The drive shift order for SGPIO unit 0 is programmed as follows: Drive 4
(first drive to be shifted), Drive 6, Drive 0, Drive 1, Drive 2, Drive 3, Drive 5, and
Drive 7 (last drive to be shifted). Note that the last six drives (0, 1, 3, 4, 5, and 7) are
not used for SGPIO unit 0, but are simply programmed in that order in Table 324,
“SGPIO Start Drive Upper Register x — SGSDURx” on page 480 . Table 314 shows the
outputs[7:0] of the multiplexer block for SGPIO unit 0.
SGPIO unit 1 supports four drives. Bit[0] in
Table 321, “SGPIO Interface Control
Register x - SGICRx” on page 475 must be set for SGPIO unit 1, as this sets up the
external pins for SGPIO mode. The drive shift order for SGPIO unit 1 is programmed as
follows: Drive 3 (first drive to be shifted), Drive 1, Drive 7, Drive 5, Drive 0, Drive 2,
Drive 4, and Drive 6 (last drive to be shifted). Note that the last four drives (0, 2, 4,
and 6) are not used for SGPIO unit 1, but are simply programmed in that order in
Table 324, “SGPIO Start Drive Upper Register x — SGSDURx” on page 480 . Table 315
shows the outputs[7:0] of the multiplexer block for SGPIO unit 1.
Table 314. Example 1: Multiplexer Block Outputs for SGPIO Unit 0 in Direct LED Mode
Multiplexer
Block
Output
Output 7 Output 6 Output 5 Output 4 Output 3 Output 2 Output 1 Output 0
Drive to
Shift
Register
a
,
b
a. The grayed cells imply that these outputs are not valid for this example, but are programmed in that manner
and yield the outputs shown.
b. This entire row is shown simply to demonstrate how the drives’ order would be mapped if the SGPIO Unit 0
were to be used in SGPIO mode.
Drive 7 Drive 5 Drive 3 Drive 2 Drive 1 Drive 0 Drive 6 Drive 4
Drive to
Direct LED
Signals
a
N/A c
c. The cells labeled “N/A” are not valid outputs for Direct LED Mode. For example, they are not connected.
N/A N/A N/A Drive 1 Drive 0 Drive 6 Drive 4
Table 315. Example 2: Multiplexer Block Outputs for SGPIO Unit 1 in SGPIO Mode
Multiplexer
Block
Output
Output 7 Output 6 Output 5 Output 4 Output 3 Output 2 Output 1 Output 0
Drive to
Shift
Register
a
a. The grayed cells imply that these outputs are not valid for this example, but are programmed in that manner
and yield the outputs shown.
Drive 6 Drive 4 Drive 2 Drive 0 Drive 5 Drive 7 Drive 1 Drive 3
Drive to
Direct LED
Signals
a,b
b. This entire row is shown simply to demonstrate how the drives’ order would be mapped if the SGPIO Unit 1
were used in Direct LED mode.
N/A c
c. The cells labeled “N/A” are not valid outputs for Direct LED Mode. For example, they are not connected.
N/A N/A N/A Drive 5 Drive 7 Drive 1 Drive 3