Intel CONTROLLERS 413808 - Manual (Page 65)

Intel ® 413808 and 413812 I/O Controllers in TPER Mode
October 2007 Developer’s Manual
Order Number: 317805-001US 65
Address Translation Unit (PCI-X)—Intel
®
413808 and 413812
ATU configuration address space starts at internal address 3100H. Therefore,
P_AD[7:2] equal to 000000
2
equates to address 3100H and P_AD[7:2] equal to
000001
2
results in address 3104H and so on.
For inbound configuration reads, IRQ and ITQ are used in the same manner as inbound
memory read operations. The internal bus cycle that results are a 32-bit transaction.
For inbound configuration writes, ATU adds a delayed write data queue (IDWQ), which
holds data the same way as the IWQ. Transaction information from the configuration
write operation on the PCI interface is captured into the IDWQ (when full, a Retry is
signaled). Data from delayed write (split write in PCI-X mode) request cycle is latched
into IDWQ and forwarded to the internal bus interface. Once transaction ordering and
priority have been satisfied, the internal bus master interface requests the internal bus
and delivers write data to the target as defined in Section 2.2.1.2 .
Status of the internal bus transaction is returned to the PCI bus, PCI initiator. When
operating in conventional PCI mode, the initiator retry cycle is accepted once the write
has been completed on the internal bus and status has been captured for return to the
PCI master. When operating in PCI-X mode, a Split Completion Message (message
class=0h and message index= 00h - Normal Completion) is generated on the PCI bus,
once the write has been completed on the internal bus and status has been latched for
return to the PCI master. Since Master Aborts and Target Aborts cannot occur during
internal configuration cycles, normal completion status is returned. Data from PCI
completion transaction is discarded.