Intel CONTROLLERS 413808 - Manual (Page 526)

Intel
®
413808 and 413812—SRAM Memory Controller
Intel ® 413808 and 413812 I/O Controllers in TPER Mode
Developer’s Manual October 2007
526 Order Number: 317805-001US
8.3.3.4 Scrubbing
Fixing the data error in memory is called scrubbing. The 4138xx relies on Intel XScale
®
processor software to perform the scrubbing. When the SMCU detects an error during a
read, the SMCU logs the address where the error occurred and interrupts the core. The
core decides how to fix the error through an interrupt handler. Software could decide to
perform the scrubbing on:
• the data location that failed
• the entire row of the data that failed
• the entire memory
For single-bit errors reported on a write transaction scrubbing is not required, as the
SMCU will have scrubbed the data during the RMW operation. For single-bit errors, the
error is fixed by reading the location that failed and writing back the data after the ECC
hardware fixed it. The scrubbing routine should read the 32-bit data using a
ld instruction and write the data back with a
st
instruction. Software should isolate
activity on the memory location to guarantee animosity.
Note: If the scrubbing routine reads the failed location in order to fix the single-bit error, a
second error will be reported. Therefore, software should disable single-bit ECC
reporting (SECCR[0]) during the scrubbing routine. Multi-bit errors cannot be fixed by
the H-Matrix.
8.3.3.4.1 ECC Example Using the H-Matrix
Assume the core writes 9ABC DEF0H to the SRAM memory space on DQ[31:0] .
Using the G-Matrix in Figure 58 , the SRAM Control Block creates each check bit by
XORing the appropriate bits in the row. Using 9ABC DEF0H, the ECC code generated is
11H. This code is written with the data to the SRAM memory on SCB[7:0] .
Assume that bit 17 was corrupted in the array. Therefore, the bit has been inverted
from 0 to 1.
At some later point in time, the core wishes to read from the same address. The core
issues a read transaction.to the SRAM memory. Upon the receipt of 9AB E DEF0H on
DQ[31:0] , the SRAM Control Block calculates the syndrome with the G-Matrix in
Figure 58 . The SRAM Control Block calculates a syndrome of 37H.
Note: During a memory write, ECC code is created by XORing the appropriate data bits’ ECC
codes indicated by the G-Matrix. The syndrome is created during a memory read by
XORing the 7-bit value generated by XORing appropriate data bits’ ECC codes indicated
by the G-Matrix with the check bits ( SCB[7:0]
)
.
Referring to Table 346 , if the syndrome is non-zero and matches a value in the
H-Matrix, there is a single-bit error that can be fixed. A syndrome of 37H matches a
value in the H-Matrix (see Figure 60 ) which indicates that bit 17 has an error. The
SRAM Control Block inverts bit 17 prior to returning the corrected data on the internal
bus. The SMCU returns 9ABC DEF0H on the internal bus.
Assuming this was the first error the SMCU records the address where the error
occurred in SECAR and error type in SELOG. If error reporting is enabled in the SECCR,
the SMCU writes a 1 to SMCISR[0] which generates an interrupt to the core. A software
interrupt handler scrubs the array and fixes the error in bit 17. Unless more errors
occur, future reads from this location do not result in an error.