Intel CONTROLLERS 413808 - Manual (Page 189)

Intel ® 413808 and 413812 I/O Controllers in TPER Mode
October 2007 Developer’s Manual
Order Number: 317805-001US 189
Address Translation Unit (PCI-X)—Intel
®
413808 and 413812
2.14.51 ATU Power Management Control/Status Register - APMCSR
Power Management Control/Status bits adhere to the definitions in the PCI Bus Power
Management Interface Specification, Revision 1.1. This 16-bit register is the control
and status interface for the power management extended capability.
Table 78. ATU Power Management Control/Status Register - APMCSR
Bit Default Description
15 0
2
PME_Status - This function is not capable of asserting the PME# signal in any state, since PME# # is not
supported by the 4138xx.
14:9 00H Reserved
8 0
2
PME_En - This bit is hard-wired to read-only 0
2
since this function does not support PME# generation
from any power state.
7:2 000000
2
Reserved
1:0 00
2
Power State - This 2-bit field is used both to determine the current power state of a function and to set
the function into a new power state. The definition of the values is:
00
2
- D0
01
2
- D1
10
2
- D2 (Unsupported)
11
2
- D3
hot
The 4138xx supports only the D0 and D3
hot
states.
PCI
IOP
Attributes
Attributes
15 12 8 4 0
ro
ro
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
ro
ro
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rw
rw
rw
rw
Attribute Legend:
RV = Reserved
PR = Preserved
RS = Read/Set
RW = Read/Write
RC = Read Clear
RO = Read Only
NA = Not Accessible
Register Offset
+09CH