Intel CONTROLLERS 413808 - Manual (Page 64)

Intel
®
413808 and 413812—Address Translation Unit (PCI-X)
Intel ® 413808 and 413812 I/O Controllers in TPER Mode
Developer’s Manual October 2007
64 Order Number: 317805-001US
2.2.1.4 Inbound Configuration Cycle Translation
The 4138xx ATU only accepts Type 0 configuration cycles with a function number of
zero when bit[7] of the ATUHTR (see Section 2.14.11, “ATU Header Type Register -
ATUHTR” on page 153 ) is cleared or function numbers of zero and one when bit[7] of
the ATUHTR is set.
The ATU is configured through the PCI bus. When operating in conventional PCI mode,
all inbound configuration cycles are processed as delayed transactions. When operating
in PCI-X mode, all inbound configuration cycles are processed as split transactions. The
translation mechanism for inbound configuration cycles is defined by the PCI Local Bus
Specification, Revision 2.3.
The ATU configuration space is selected by a PCI configuration command and claims
access (by asserting P_DEVSEL# ) when the P_IDSEL pin is asserted, the PCI
command indicates a configuration read or write, and address bits P_AD[1:0] are 00
2 all during the address phase. The ATU interface ignores any configuration command
( P_IDSEL active) where P_AD[1:0] are not 00
2
(e.g. Type 1 commands). During the
configuration access address phase, the PCI address is divided into a number of fields
to determine the actual configuration register access. These fields, in combination with
the byte enables during the data phase create the unique encoding necessary to access
the individual registers of the configuration address space:
• P_AD[7:2] - Register Number. Selects one of 64 DWORD registers in the ATU PCI
configuration address space.
• P_C/BE[3:0]# - Used in data phase. Selects which actual configuration register is
used within the DWORD address. Creates byte addressability of the register space.
• P_AD[10:8] - Function Number. Used to select which function of a multi-function
device is being accessed. The ATU is function 0 and therefore it only responds to
000
2
in this bit field and ignore all other bit combinations.
• P_AD[27:24] - Upper Register Number. In PCI-X Mode 2, Upper Register Number
and Lower Register Number combine to select one of 1024 DWORD registers in the
ATU PCI configuration address space.
Note: In PCI-X Mode 2, the ATU does not support any extended capabilities list items starting
at offset 100H indicated by a Null Enhanced Capability Header at offset 100H (i.e.,
Enhanced Capability Header with a Capability ID of 0000H, a Capability Version of 0H,
and a Next Capability offset of 000H).