Intel CONTROLLERS 413808 - Manual (Page 493)

Intel ® 413808 and 413812 I/O Controllers in TPER Mode
October 2007 Developer’s Manual
Order Number: 317805-001US 493
System Controller (SC) and Internal Bus Bridge—Intel
®
413808 and 413812
7.3.5 Ordering and Passing Rules
Table 333 lists the ordering and passing rules requirements for the bridge. Although
write requests and write data completions are completely independent transactions on
the internal bus, the bridge internally combines a write request with its corresponding
write data transaction when enqueuing write requests and when issuing write requests.
For example, a write request made to the target side of the bridge is not considered
valid in the bridge until the write request and the data for that write request have been
received. Similarly, a write request mastered by the bridge is not considered done until
the write request and the write data completion have been executed on the internal
bus. For that reason, Table 333 shows a write request (Addr(Wr)) and a write data
completion (Data(Wr)) as one entity.
— Addr(Wr) — Write Address Request
— Addr(Rd) — Read Address Request
— Data(Rd) — Read Data Completion
— Data(Wr) — Write Data Completion
7.3.5.1 Strong Ordering Rule Requirements
This rule applies for Write Requests targeting only the north interface of the Bridge. For
example, outbound write requests from the north internal bus to the south internal
bus. Although the bridge must allow write requests to pass read requests as shown in
Table 333 (Row 1, Column 2), to maintain data coherency the bridge does not allow
enqueuing a write request whose cacheline address matches that of a previously
enqueued read request. The write request is retried on the north internal bus until the
read request has been retired. For example, the data for the read request has been
returned.
Note: The south interface of the South Bridge does not follow the Strong Ordering Rule
Requirements described in
Section 7.3.5.1, Strong Ordering Rule Requirements
.
Table 333. Ordering and Passing Rules for both Inbound and Outbound Transactions
Row Pass Column?
Addr(Wr)/Data(Wr)
(Column 1)
Addr(Rd)
(Column 2)
Data(Rd)
(Column 3)
Addr(Wr)/Data(Wr)
(Row 1)
No
(Row 1, Column 1)
Yes a
(Row 1, Column 2)
a. Strong Ordering Rule Requirements for Outbound Write Requests in order to maintain data coherency. Refer
to Section 7.3.5.1, Strong Ordering Rule Requirements .
Yes/No
(Row 1, Column 3)
Addr(Rd)
(Row 2)
No
(Row 2, Column 1)
No
(Row 2, Column 2)
Yes/No
(Row 2, Column 3)
Data(Rd)
(Row 3)
No
(Row 3, Column 1)
Yes
(Row 3, Column 2)
Yes/No
(Row 3, Column 3)
No - The row is
not
allowed to pass the column
Yes - The row must be allowed to pass the column
Yes/No - There are no requirements