Intel CONTROLLERS 413808 - Manual (Page 248)

Intel
®
413808 and 413812—Address Translation Unit (PCI Express)
Intel ® 413808 and 413812 I/O Controllers in TPER Mode
Developer’s Manual October 2007
248 Order Number: 317805-001US
The translation portion of outbound ATU transactions is accomplished with a value
register in the same manner as inbound translations. Each outbound memory window
is associated with one translation register which provides the upper translation
addresses (OUMWVR0-3). When the corresponding OUMWVRx register is all-zero a
3DW header transaction is generated on the PCI Express Link. Otherwise, a 4DW
header is generated on the PCI Express Link using the value in the OUMWVRx register
for the upper 32-bit address. ATU uses the following registers during outbound address
translation:
• Outbound Upper 32-bit Memory Window Value Register 0 (OUMWVR0)
• Outbound Upper 32-bit Memory Window Value Register 1 (OUMWVR1)
• Outbound Upper 32-bit Memory Window Value Register 2(OUMWVR2)
• Outbound Upper 32-bit Memory Window Value Register 3(OUMWVR3)
• Outbound I/O Window Value Register (OIOWVR)
• Outbound Configuration Cycle Address Register (OCCAR)
See Section 3.17 for details on outbound translation register definition and
programming constraints.
The translation algorithm used, as stated, is very similar to inbound translation. For
memory transactions, the algorithm is:
For memory transactions, the internal bus address is bitwise ANDed with the inverse of
4 Gbytes which clears the upper 4 bits of the 36 bit address. The result is bitwise ORed
with the outbound upper window value register left shifted by 32 to create the Upper
32-bits of the PCI address. When the Upper 32-bits of the PCI Address equals
0000 0000H, the ATU generates a transaction with a 3DW header on the PCI Express
Link, otherwise, a 4DW header is used.
For I/O transactions, the algorithm is:
For I/O transactions, the internal bus address is bitwise ANDed with the inverse of 64
Kbytes which clears the upper 20 bits of address. Address aliasing is prevented by the
outbound window value registers which only allow values on boundaries equivalent to
the window’s length.
Equation 10.Outbound Address Translation
PCI Address = (Internal_Bus_Address & 0.FFFF.FFFFH) | (Upper_Window_Value_Register << 32)
Equation 11.I/O Transactions
PCI Address = (Internal_Bus_Address & 0.0000.FFFFH) | Window_Value_Register