Intel CONTROLLERS 413808 - Manual (Page 106)

Intel
®
413808 and 413812—Address Translation Unit (PCI-X)
Intel ® 413808 and 413812 I/O Controllers in TPER Mode
Developer’s Manual October 2007
106 Order Number: 317805-001US
2.7.3.10 Split Completion Messages
As a target, the ATU may encounter this error when operating in the PCI-X mode.
Uncorrectable Data errors occurring during Split Completion Messages claimed by the
ATU may assert PERR# (when enabled) or SERR# (when enabled) on the PCI Bus.
When an error occurs, the ATU accepts the data and complete normally. Specifically,
the following actions with the given constraints are taken by the ATU:
• PERR# is asserted three clocks cycles following the data phase in which the
uncorrectable data error is detected on the bus. This is only done when the Parity
Error Response bit in the ATUCMD is set. When the ATU asserts PERR# , additional
actions are taken:
— The Master Parity Error bit in the ATUSR is set.
— When the ATU PCI Master Parity Error Interrupt Mask Bit in the ATUIMR is clear,
set the PCI Master Parity Error bit in the ATUISR. When set, no action.
— When the SERR# Enable bit in the ATUCMD is set, and the Uncorrectable Data
Error Recover Enable bit in the PCIXCMD register is clear, assert SERR# ;
otherwise no action is taken. When the ATU asserts SERR#, additional actions
are taken:
Set the SERR# Asserted bit in the ATUSR.
When the ATU SERR# Asserted Interrupt Mask Bit in the ATUIMR is clear, set
the SERR# Asserted bit in the ATUISR. When set, no action.
When the ATU SERR# Detected Interrupt Enable Bit in the ATUCR is set, set
the SERR# Detected bit in the ATUISR. When clear, no action.
• When the SCE bit (Split Completion Error -- bit 30 of the Completer Attributes) is
set during the Attribute phase, the Received Split Completion Error Message bit in
the PCIXSR is set. When the ATU sets this bit, additional actions are taken:
— When the ATU Received Split Completion Error Message Interrupt Mask bit in
the ATUIMR is clear, set the Received Split Completion Error Message bit in the
ATUISR. When set, no action.
• The Detected Parity Error bit in the ATUSR is set. When the ATU sets this bit,
additional actions are taken:
— When the ATU Detected Parity Error Interrupt Mask bit in the ATUIMR is clear,
set the Detected Parity Error bit in the ATUISR. When set, no action.
• For PCI-X Mode 2, update the “ECC Control and Status Register - ECCCSR” on
page 195 , the “ECC First Address Register - ECCFAR” on page 198 , the “ECC
Second Address Register - ECCSAR” on page 199 , and the “ECC Attribute Register -
ECCAR” on page 200 for the transaction.
• The transaction associated with the Split Completion Message is discarded.
• When the discarded transaction was a read, the read completion is aborted on the
internal bus of the 4138xx.