Intel CONTROLLERS 413808 - Manual (Page 534)

Intel
®
413808 and 413812—SRAM Memory Controller
Intel ® 413808 and 413812 I/O Controllers in TPER Mode
Developer’s Manual October 2007
534 Order Number: 317805-001US
8.5 Parity Interrupts/Error Conditions
If a data parity error is detected on any of the SMCU ports and parity is enabled, the
SMCU records the requesting port that detected the parity error in the SPCSR[19:16]
and interrupts the core. Refer to the Section 8.6.8, “SRAM Parity Control and Status
Register — SPARCSR” on page 542
When the SMCU detects a parity error, the SMCISR[8] is set to 1. Whenever the SMCU
toggles the SMCUSR[8] bit from 0 to 1, an interrupt is generated to the core.