Intel CONTROLLERS 413808 - Manual (Page 89)

Intel ® 413808 and 413812 I/O Controllers in TPER Mode
October 2007 Developer’s Manual
Order Number: 317805-001US 89
Address Translation Unit (PCI-X)—Intel
®
413808 and 413812
These transaction ordering rules define the way idata moves in both directions through
the ATU. In Table 13 and Table 14 a NO response in a box means that based on
ordering rules, the current transaction (the row) can not pass the previous transaction
(the column) under any circumstance. A Yes response in the box means that the
current transaction is allowed to pass the previous transaction but is not required to,
based on whether a consistent view of data or prevention of deadlocks is needed.
In the case of inbound write operations, multiple transactions may exist within the IWQ
and the corresponding IWADQ at any point in time. The ordering of these transactions
is based on a time stamp basis. Transactions entering the queue are stamped with a
relative time in relation to all other transactions moving in a similar direction.
In Example 1 on page 89 , the inbound write and outbound read queues of the ATU are
shown. In this example, transaction A entered the write queue at Time 0 . Next, the
ATU entered read data into the outbound read queue at Time 1 (Transaction B). Finally,
before the previous transactions could be cleared, another inbound write, Transaction
C, was entered into the IWQ. The ordering in Table 13 states that nothing can pass an
inbound write and therefore Transaction A must complete on the internal bus before
Transaction B since an outbound read completion can not pass an inbound write. Also,
Transaction A must complete before Transaction C since an inbound write can not pass
another inbound write. Once Transaction A completes, Transaction C moves to the head
of the IWQ. The two transactions at the head of the queues moving data in an inbound
direction are now Transaction C, an inbound write, and Transaction B, an outbound read
completion. Ordering states that an inbound write may pass an outbound read
completion. This means that the arbitration mechanism now takes over to decide which
completes. Note that ordering enforced the completion of Transaction A but arbitration
dictated the completion of Transactions B and C.
The first action performed to determine which transaction is allowed to proceed (either
inbound or outbound) is to apply the rules of ordering as defined in Table 13 and
Table 14 . Any box marked No must be satisfied first. For example, when an inbound
read request is in ITQ and it was latched after the data in the IDWQ arrived (this is a
configuration write), then ordering states that an Inbound Read Request may not pass
an Inbound Configuration Write Request. Therefore, the Inbound Configuration Write
Request must be cleared out of IDWQ before the Inbound Read Request is attempted
on the internal bus. Once transaction ordering is satisfied, the boxes marked Yes are
now resolved.
Example 1. Inbound Queue Completion
A6499-01
Outbound Read Queue
B B B B B B B B
Inbound Write Queue
C C C C C C C C A A A A A A A
Outbound Read Queue
B B B B B B B B
Inbound Write Queue
C C C C C C C C
PCI Bus Internal Bus