Intel CONTROLLERS 413808 - Manual (Page 777)

Intel ® 413808 and 413812 I/O Controllers in TPER Mode
October 2007 Developer’s Manual
Order Number: 317805-001US 777
Clocking and Reset—Intel ® 413808 and 413812
17.3 Reset Pins
Table 515. Reset Pin Summary
Pin Input/Output Description
P_RST# Input
Primary chip reset. Should be connected to PCI RST#
or PCI Express PERST# depending on the mode of
operation.
WARM_RST# Input
Warm Reset is the same as a cold reset, except sticky
configuration bits are not reset. This pin should only
be used when the sticky bit functionality is required.
In this scenario, the WARM_RST# pin must be tied to
the system reset PCI_RST# signal while the P_RST#
pin can be tied to the system power good signal. When
the sticky bit functionality is not required, the
WARM_RST# pin should not be used and must be tied
to Vcc. When the PCI Express interface is used as an
endpoint, the PCI Express inband Hot Reset
Mechanism can also be used to provide the sticky bit
functionality.
Note: Driving WARM_RST# using any other
methods than suggested above may result in
unpredictable behavior of the device.
P_RSTOUT# Output
Secondary Reset. This is used as the PCI bus reset
when operating as the Central Resource
PB_RSTOUT# Output
Peripheral Bus Reset: This signal is asserted whenever
the internal logic is reset.
PCI Express Hot Reset n/a
This is an inband reset message that can be received
as an endpoint, and generated as a root complex.