Address translation unit (pci express)—intel, Bit default description, Intel – Intel CONTROLLERS 413808 User Manual

Page 367

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Intel

413808 and 413812 I/O Controllers in TPER Mode

October 2007

Developer’s Manual

Order Number: 317805-001US

367

Address Translation Unit (PCI Express)—Intel

413808 and 413812

3.17.87 Power Budgeting Enhanced Capability Header - PWRBGT_CAPID

This register defines the power budgeting capability identifier.

3.17.88 Power Budgeting Data Select Register - PWRBGT_DSEL

This register defines the power budgeting capability identifier.

Table 227. Power Budgeting Enhanced Capability Header - PWRBGT_CAPID

Bit

Default

Description

31:20

000H

Next PCI Express Extended Capability Pointer: This is the last capability.

19:16

Power Budgeting Capability Version Number: PCI Express Power Budgeting Capability Version Number.

15:0

0004H

Power Budgeting Capability ID: PCI Express Power Budgeting Capability ID indicating Advanced Error

Reporting Capability.

PCI

IOP

Attributes

Attribute Legend:

RV = Reserved

PR = Preserved

RS = Read/Set

RW = Read/Write

RC = Read Clear

RO = Read Only

NA = Not Accessible

Internal Bus Address Offset

+1F0H

Table 228. Power Budgeting Data Select Register - PWRBGT_DSEL

Bit

Default

Description

31:8

00_0000H Preserved

7:0

00H

Data Select: This read-write register indexes the Power Budgeting Data reported through the Data

values for this register start at 0 to select the first DWORD of Power Budgeting Data; subsequent

DWORDs of Power Budgeting Data are selected by increasing index values. A value of 0 selects the

DWORD data starting at address 0x314 to appear in the data register at offset 0x308, a value of 1

selects the DWORD data starting at address 0x318 to appear in the in the data registers at offset 0x308

and so on. Values greater than 23 for this register reports all zeros in the data register.

PCI

IOP