Intel
®
413808 and 413812—Contents
Intel
®
413808 and 413812 I/O Controllers in TPER Mode
Developer’s Manual
October 2007
22
Order Number: 317805-001US
54 4138xx SGPIO Unit 1 Pin Mapping ............................................................................473
55 Typical Internal Bus System Controller Block Diagram .................................................488
56 Intel
®
413808 and 413812 I/O Controllers in TPER Mode SRAM Memory Controller Block
Diagram513
57 ECC Write Flow ......................................................................................................520
58 Intel
®
413808 and 413812 I/O Controllers G-Matrix (generates the ECC) .....................521
59 ECC Read Data Flow ...............................................................................................523
60 4138xx H-Matrix (indicates the single-bit error location)..............................................524
61 Logical Data Access Paths with Parity Protection .........................................................528
62 The Peripheral Bus Interface Unit..............................................................................545
63 Data Width and Low Order Address Lines...................................................................548
64 Sixty-Four Mbyte Flash Memory System ....................................................................550
65 120 ns Flash Single Transfer Read Cycle....................................................................551
66 120 ns Flash Burst Read Cycle..................................................................................552
67 120 ns Flash Single Write Cycle
1
..............................................................................553
68 Interrupt Controller Block Diagram (Active Interrupt Source Registers)..........................573
69 Interrupt Controller Block Diagram (FIQ/IRQ Interrupt Vector Generation) .....................574
70 Intel
®
413808 and 413812 I/O Controllers in TPER Mode Interrupt Controller Connections....
575
71 Programmable Timer Functional Diagram...................................................................627
72 Timer Unit State Diagram ........................................................................................632
73 Basic SMBus Transfer Waveform...............................................................................645
74 Start (S) / Repeat Start (Sr) Signaling ......................................................................645
75 Stop (P) Signaling ..................................................................................................646
76 ACK (A) Signaling...................................................................................................646
77 NACK (N) Signaling.................................................................................................646
78 DWORD Configuration Read Protocol (SMBus Block Write/Block Read, PEC Enabled)........649
79 DWORD Memory Read Protocol (SMBus Block Write/Block Read, PEC Enabled) ...............650
80 DWORD Configuration Read Protocol (SMBus Word Write/Word Read, PEC Enabled) ........650
81 DWORD Configuration Read Protocol (SMBus Block Write/Block Read, PEC Disabled) .......650
82 DWORD Memory Read Protocol (SMBus Block Write/Block Read, PEC Disabled)...............650
83 DWORD Configuration Read Protocol (SMBus Word Write/Word Read, PEC Disabled) .......651
84 DWORD Memory Read Protocol (SMBus Word Write/(Word, Byte) Read, PEC Enabled).....651
85 DWORD Memory Read Protocol (SMBus Word Write/Byte Read, PEC Enabled).................651
86 DWORD Configuration Write Protocol (SMBus Block Write, PEC Enabled)........................652
87 DWORD Memory Write Protocol (SMBus Word Write, PEC Enabled)................................652
88 DWORD Configuration Write Protocol (SMBus Byte Write, PEC Enabled) .........................653
89 Example UART Data Frame ......................................................................................662
90 NRZ Bit Encoding Example – (0100 1011)..................................................................662
91 I
2
C Bus Configuration Example.................................................................................690
92 I
2
C Bus Interface Unit Block Diagram........................................................................692
93 Start and Stop Conditions........................................................................................695
94 START and STOP Conditions.....................................................................................696
95 Data Format of First Byte in Master Transaction..........................................................698
96 Acknowledge on the I
2
C Bus ....................................................................................699
97 Clock Synchronization During the Arbitration Procedure...............................................700
98 Arbitration Procedure of Two Masters ........................................................................701
99 Master-Receiver Read from Slave-Transmitter............................................................704
100 Master-Receiver Read from Slave-Transmitter / Repeated Start /Master-Transmitter Write to
Slave-Receiver704
101 A Complete Data Transfer........................................................................................704
102 Master-Transmitter Write to Slave-Receiver ...............................................................706
103 Master-Receiver Read to Slave-Transmitter................................................................706
104 Master-Receiver Read to Slave-Transmitter, Repeated START, Master-Transmitter Write to
Slave-Receiver706