1 uart x receive buffer register, 2 uart x transmit holding register, 447 uart x receive buffer register - (uxrbr) – Intel CONTROLLERS 413808 User Manual

Page 670: 448 uart x transmit holding register - (uxthr), Intel, Bit default description, Unit # 01 intel xscale

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413808 and 413812—UARTs

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413808 and 413812 I/O Controllers in TPER Mode

Developer’s Manual

October 2007

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13.4.1

UART x Receive Buffer Register

In non-FIFO mode, this register holds the character(s) received by the UART Receive

Shift register. When it receives fewer than eight bits, the bits are right-justified and the

leading bits are zeroed. Reading the register empties the register and resets the data

ready (DR) bit in the Line Status register to 0. Other (error) bits in the Line Status

byte(s) at the bottom of the FIFO.
When the UART is in eight-bit Peripheral Bus mode, the 24 most significant bits must be

ignored and not used. Reading these bits returns unpredictable results.

13.4.2

UART x Transmit Holding Register

This register holds the next data byte(s) to be transmitted. When the Transmit Shift

the Shift register and the Transmit Data Request (TDRQ) bit in the Line Status register

is set to one (see

Table 451, “Interrupt Identification Register Decode” on page 673

In FIFO mode, writing to THR puts data to the top of the FIFO. The data at the bottom

of the FIFO is loaded to the Shift register when it is empty. In eight-bit Peripheral

mode, the 24 most significant bits are ignored and is not transmitted.

Table 447. UART x Receive Buffer Register - (UxRBR)

Bit

Default

Description

31:8

00h

Reserved

7:0

00h

Data Byte

Unit #

Intel XScale

Core internal bus address

+2300H (DLAB=0)

+2340H (DLAB=0)

Attribute Legend:

RV = Reserved

PR = Preserved

RS = Read/Set

RW = Read/Write

RC = Read Clear

RO = Read Only

NA = Not Accessible

Table 448. UART x Transmit Holding Register - (UxTHR)

Bit