Intel CONTROLLERS 413808 - Manual (Page 87)

Intel ® 413808 and 413812 I/O Controllers in TPER Mode
October 2007 Developer’s Manual
Order Number: 317805-001US 87
Address Translation Unit (PCI-X)—Intel
®
413808 and 413812
2.6.3 Transaction Ordering
Because the ATU can process multiple transactions, they must maintain proper
ordering to avoid deadlock conditions and improve throughput. The ATU transaction
ordering rules used by the 4138xx are listed in Table 13 for the inbound direction and
Table 14 on page 88 for the outbound direction. The tables are based on the direction
the transaction is moving, i.e. the data for outbound delayed read moves in the same
direction as the data for an inbound write or the address/command for an inbound
read. When operating in the PCI-X mode, the ATU ignores the Relaxed Ordering
Attribute.
Note: Outbound Non-Posted Writes are the result of Internal Bus Memory writes that are
claimed by either the I/O translation window or the Outbound Configuration Cycle Data
Register - OCCDR . Though these write requests arrive on the PCI bus as non-posted
write requests, it is important to note that from the Intel XScale
®
processor point of
view, these internal bus memory write requests are posted into the Outbound ATU
transaction queue. Furthermore, in PCI-X mode non-posted write requests have the
potential to be split. Thus, even though a split write completion may be returned to the
ATU on the PCI bus for a given outbound non-posted write request, the split write
completion does not passed back through to the internal bus. Additionally, strong
ordering between outbound memory (posted) write requests and outbound non-posted
write requests are
not
maintained as indicated in Table 14 on page 88 .
For best performance, the user should designate the two Outbound Memory Windows
as non-cacheable and bufferable from the Intel XScale
®
processor. This assignment
enables the Intel XScale
®
processor to issue multiple outstanding transactions to the
Outbound Memory Windows, thereby, taking full advantage of the ATU outbound queue
architecture. However, the user needs to be aware that the Outbound ATU queue
architecture does not maintain strict ordering between read and write requests as
described in Table 14, “ATU Outbound Data Flow Ordering Rules” on page 88 . In the
event that the user requires strict ordering to be maintained, the user must change the
designation of this region of memory to be non-cacheable/non-bufferable and enforce
the requirement in software.
Table 13. ATU Inbound Data Flow Ordering Rules
Row Pass Column?
a
a. Outbound Non-Posted Write Completions are not included in this table since these transactions are never
passed back to the Internal Bus Requester (Intel XScale ® processor). The reason is that from the Intel XScale ®
processor’s point of view, these write requests are posted into the Outbound ATU transaction queue.
ATU Inbound
Writes
Inbound
Delayed
Read
Request
(PCI mode)
Inbound
Split Read
Request
(PCI-X
mode)
Inbound
Configuration
Write
Request
Outbound
Split Read
Completion
ATU Inbound Writes No Yes Yes Yes Yes
Inbound Delayed Read
Request (PCI mode)
No No NA No Yes
Inbound Split Read
Request (PCI-X mode)
No NA No No Yes
Inbound Configuration
Write Request
No No No NA Yes
Outbound Split Read
Completion
No Yes Yes Yes Yes