Intel CONTROLLERS 413808 - Manual (Page 492)

Intel
®
413808 and 413812—System Controller (SC) and Internal Bus Bridge
Intel ® 413808 and 413812 I/O Controllers in TPER Mode
Developer’s Manual October 2007
492 Order Number: 317805-001US
7.3.4 Bridge Memory Window
The North Internal Bus interface of the Bridge performs subtractive decoding. For
example, transactions on the north internal bus that are not claimed by other targets
on the north internal bus are claimed by the Bridge North Interface.
The South Bridge Interface performs positive decoding. The Bridge provides a Bridge
Memory Window defined by the Bridge Window Base Address Register — BWBAR and
the Bridge Limit Register — BWLR . Transactions on the south internal bus that target
this memory window are claimed and forwarded to the north internal bus. The South
Bridge Interface also claims transactions that target the Bridge memory-mapped
registers. The memory-mapped registers are only accessible from the south internal
bus. For example, transactions to the Bridge memory-mapped registers by the Intel
XScale
®
processors that reside on the north internal bus, are propagated from the
north internal bus to the south internal bus via the Bridge, and then claimed by the
Bridge on the south interface.
Note: For bridge memory window access overlapping the bridge memory-mapped register
space (+1780 through +17FFH), the bridge memory window is not accessible, and the
bridge memory-mapped register space is addressed.