Intel CONTROLLERS 413808 - Manual (Page 786)

Intel ® 413808 and 413812—Test Logic Unit and Testability
Intel ® 413808 and 413812 I/O Controllers in TPER Mode
Developer’s Manual October 2007
786 Order Number: 317805-001US
18.2.2.1 Test-Logic-Reset State
In this state, test logic is disabled to allow normal operation of the Intel XScale
®
processor. This is achieved by loading the instruction register with the IDCODE
instruction. No matter what he state of the controller, it enters Test-Logic-Reset state
when the TMS input is held high for at least five rising edges of TCK . The controller
remains in this state while TMS is high. The TAP controller is also forced to enter this
state by enabling TRST# .
When the controller exits the Test-Logic-Reset controller state as a result of an
erroneous low signal on the TMS line at the time of a rising edge on TCK (for example,
a glitch due to external interference), it returns to the Test-Logic-Reset state following
three rising edges of TCK with the TMS line at the intended high logic level. Test logic
operation is such that no disturbance is caused to on-chip system logic operation as the
result of such an error.
Transition to next state: On the rising edge of
TCK , when TMS is low move to
Run-Test/Idle, else TMS remains high so stay in Reset.
18.2.2.2 Run-Test/Idle State
This state is a controller state between scan operations. The controller remains in this
state as long as TMS is held low. In the Run-Test/Idle state, activity in selected test
logic occurs only when certain instructions are present. For example, the RUNBIST
instruction causes on-chip self-tests to execute in this state. Instructions that do not
cause functions to execute generate no activity in the test logic while the controller is in
this state.
The instruction register and all test data registers retain their current value in this
state.
Transition to next state: When
TMS is high on the rising edge of TCK , move to
Select-DR-Scan, else remain in Idle.
18.2.2.3 Select-DR-Scan State
This is a temporary controller state. Here the decision is made to enter the Capture-DR
column and initiate a scan sequence for the selected test data register.
All test data registers selected by the current instruction retain their previous value in
this state.
Transition to next state: When
TMS is low on the rising edge of TCK , move to
Capture-DR, else move to Select-IR.
18.2.2.4 Capture-DR State
When the controller is in this state data is parallel-loaded into test data registers
selected by the current instruction on the rising edge of TCK . Test data registers that
do not have parallel inputs are not changed. Also when capturing is not required for the
selected instruction, the register retains its previous state.
The instruction does not change while the TAP controller is in this state.
Transition to next state: When
TMS is low on the rising edge of TCK , move to Shift-DR,
else move to Exit1-DR.