Intel CONTROLLERS 413808 - Manual (Page 822)

Intel ® 413808 and 413812—Peripheral Registers
Intel ® 413808 and 413812 I/O Controllers in TPER Mode
Developer’s Manual October 2007
822 Order Number: 317805-001US
Pro
gra
mm
ab
le
Tim
ers
U
nit
Timer Mode Register 0
CP6 9
Register 0
Timer Mode Register 1 Register 1
Timer Count Register 0 Register 2
Timer Count Register 1 Register 3
Timer Reload Register 0 Register 4
Timer Reload Register 1 Register 5
Timer Interrupt Status Register Register 6
Watch Dog Timer Control Register Register 7
Watch Dog Timer Setup Register Register 8
Undefined Register 9–15
Bu
s I
nte
rfa
ce
U
nit
L2 Cache and BIU Error Logging Register
CP7 2
Register 0
L2 Cache and BIU Error Lower Address Register Register 1
L2 Cache and BIU Error Upper Address Register Register 2
Undefined Register 3–15
Clo
ck
an
d P
ow
er
Ma
na
ge
me
nt
Un
it
Undefined
CP14 0
Register 0–5
Core Clock Configuration Register Register 6
Power Mode Register Register 7
Transmit Register Register 8
Receive Register Register 9
Debug Control and Status Register Register 10
Trace Buffer Register Register 11
Checkpoint 0 Register Register 12
Checkpoint 1 Register Register 13
Transmit/Receive Control Register Register 14
Undefined Register 15
Table 549. Coprocessor Register Locations (Sheet 3 of 4)
Peripheral Register Description (Name) Coprocessor Field CR
m
Coprocessor
Register
(Field CR
n
)