Intel CONTROLLERS 413808 - Manual (Page 74)

Intel
®
413808 and 413812—Address Translation Unit (PCI-X)
Intel ® 413808 and 413812 I/O Controllers in TPER Mode
Developer’s Manual October 2007
74 Order Number: 317805-001US
2.2.4 Outbound Read Transaction
An outbound read transaction is initiated by the Intel XScale
®
processor
5
or an ADMA
channel and is targeted at a PCI slave on the PCI bus. The read transaction is
propagated through the outbound transaction queue (OTQ) and read data is returned
through the outbound read queue (ORQ).
The ATUs internal bus target interface claims the Memory Read Dword and Memory
Read Block and Alias to Memory Read Block transaction and forwards the read request
through to the PCI bus and returns the read data to the internal bus.
The data flow for an outbound read transaction on the internal bus is summarized in
the following statements:
• For Single Address Cycles (SACs), the ATU internal bus interface latches the
internal bus address when the address is inside an outbound address translation
window and OTQ is not full. For Dual Address Cycles (DACs), ATU internal bus
target interface latches the address from the internal bus into OTQ irrespective of
the address. All read transactions are handled as split transactions. When OTQ is
full (previous outbound transactions in progress), the internal bus interface signals
a Retry to the transaction initiator.
• When during the completion cycle on the PCI interface, a master abort is
encountered, a flag is set and the ATU aborts the completion to the internal bus
requester. The OTQ is cleared of the transaction.
• When during the completion cycle on the PCI interface, a target abort is
encountered, a flag is set and the ATU aborts the completion to the internal bus
requester. The OTQ is cleared of the transaction.
• Once the transaction completes on the PCI bus, the ATU generates a split
completion transaction to return data to the internal bus requester.
• When operating in the PCI-X mode, ATU may receive a split completion error
message when attempting to read data on the PCI bus. In this case, ATU notifies
the internal bus requester about the error by aborting the completion to the
internal bus requester. The OTQ is cleared of the transaction.
The data flow for an outbound read transaction on the PCI bus is summarized in the
following statements:
• The ATU PCI interface requests the PCI bus when the head of the OTQ has at least
one entry and the ordering rules are satisfied. Once the bus is granted, the PCI
interface transfers the PCI translated address from the OTQ to the PCI bus and wait
for the transaction to be claimed.
• When no DEVSEL# is asserted, a master abort is signaled. This is passed through
to the internal bus target interface.
• When a target abort is signaled from the PCI target, the target abort is returned to
the internal bus and the PCI interface returns to idle.
• When operating in the PCI-X mode the read transaction may terminate as a split
response termination. Then the ATU receives data during the corresponding split
completion transaction. When an error occurs, the ATU may receive a split
completion error message.
5. For best performance, designate the two Outbound Memory Windows as non-cacheable and
bufferable from the Intel XScale
®
processor. This assignment enables the Intel XScale
®
processor
to issue multiple outstanding transactions to the Outbound Memory Windows, thereby, taking full
advantage of ATU outbound queue architecture. However, be aware that the Outbound ATU queue
architecture does not maintain strict ordering between read and write requests as described in
Table 14, “ATU Outbound Data Flow Ordering Rules” on page 88 . In the event that the user
requires strict ordering to be maintained, the user must change the designation of this region of
memory to be non-cacheable/non-bufferable and enforce the requirement in software.