Intel CONTROLLERS 413808 - Manual (Page 769)

Intel ® 413808 and 413812 I/O Controllers in TPER Mode
October 2007 Developer’s Manual
Order Number: 317805-001US 769
Clocking and Reset—Intel ® 413808 and 413812
17.1.2 Clocking Region Summary
Table 511 summarizes all of the input clock pins, output clock pins, and clock strapping
option pins used in 81348.
Table 511. Clock Pin Summary
Pin Input/Output Description
P_CLKIN Input PCI Bus Input Clock: Provides timing for all PCI transactions
REFCLKP
REFCLKN
Input PCI Express Input Clock: Differential 100 MHz Clock
P_M66EN Input PCI 66 MHz enable.
TCK Input
Test Clock: provides clock input for IEEE 1149.1 Boundary Scan Testing
(JTAG).
HS_FREQ[1:0] /
CR_FREQ[1:0]
Strap/Output
Hot-Swap Frequency: While in Hot-Swap mode ( HS_SM# = 0 and
PCIX_EP# = 0), these pins are inputs which determine the PCI bus
mode and frequency. See Section 17.1.1.2, “Clocking Region 2 (PCI)” on
page 764 for more details.
Central Resource Frequency: While operating in Central Resource
Mode ( PCIX_EP# = 1), these pins are outputs which control an external
PCI-X clock generator.
P_CLKOUT Output
PCI Bus Output Clock: When REFCLKN / REFCLKP are used, the IO
Processor can generate the PCI output clocks. This pin would then be
connected to P_CLKIN and trace length matched to P_CLKO[3:0] .
The P_CLKOUT and P_CLKO[3:0] outputs are enabled when the PCI-X
Interface is operating as a central resource ( PCIX_EP# = 1) and the
PCI Express input clock is used as the primary clock input
( CLK_SRC_PCIE# = 0). See Section 17.1.1.2.4, “Secondary Clock
Outputs” on page 767 for more details.
P_CLKO[3:0] Output
PCI Bus Output Clocks: When REFCLKN / REFCLKP are used, the I/O
processor can generate the PCI output clocks. These pins then provide
the PCI clocks to devices on the PCI bus.
The P_CLKOUT and P_CLKO[3:0] outputs are enabled when the PCI-X
Interface is operating as a central resource ( PCIX_EP# = 1) and the
PCI Express input clock is used as the primary clock input
( CLK_SRC_PCIE# = 0). See Section 17.1.1.2.4, “Secondary Clock
Outputs” on page 767 for more details.
SCL[2:0] Input/Output
I 2 C Clock: These are bi-directional Open Drain clocks that provides for
synchronous operation of the I 2 C buses.
SMBCLK Input/Output
SMBus Output Clock: Bi-directional open-drain clock that provides for
synchronous operation of the SMBus.
CLK_SRC_PCIE# Strap
Selects the clock source used to drive the internal logic and Intel
XScale ® processor.
0 = Source clock is the PCI Express reference clock
( REFCLKN / REFCLKP ). Note that if this selection is made, the
REFCLKN / REFCLKP must be provided regardless of the PCI
Express interface mode: Endpoint or Root Complex.
1 = Source clock is the PCI input clock ( P_CLKIN ). Note that if this
selection is made, the P_CLKIN must be provided regardless of the
PCI-X interface mode: Endpoint or Central Resource.
Note: CLK_SRC_PCIE# is not sampled during a WARM Reset.
MEM_FREQ[1:0] Strap
Memory Frequency: Determines the frequency of the DDR2 SDRAM
memory subsystem.
MEM_FREQ[1:0]
00 Reserved
01 Reserved
10 DDR-II SDRAM @ 533 MHz
11 DDR-II SDRAM @ 400 MHz (default)
PCIXM1_100# Strap
PCI-X Mode 1 100 MHz Enable: When operating as the Central
Resource ( PCIX_EP# = 1) this strap limits the PCI-X bus to 100 MHz
when operating in Mode 1.
PCIXM2_100# Strap
PCI-X Mode 2 100 MHz Enable: When operating as the Central
Resource ( PCIX_EP# = 1) this strap limits the PCI-X bus to 100 MHz
when operating in Mode 2.