Intel CONTROLLERS 413808 - Manual (Page 770)

Intel ® 413808 and 413812—Clocking and Reset
Intel ® 413808 and 413812 I/O Controllers in TPER Mode
Developer’s Manual October 2007
770 Order Number: 317805-001US
17.2 Reset Overview
17.2.1 Fundamental Reset
There are four fundamental (hardware) resets for the 81348. The main power on reset
is controlled through the PCI reset signal ( P_RST# ). When this signal is asserted, the
entire I/O Processor is placed in a reset state. The other resets have differing behavior
based on strapping options and chip mode. The reset straps are sampled at the exit of
all fundamental resets.
• P_RST# — This is an asynchronous input pin which resets the entire chip. All reset
straps are sampled at the rising edge of P_RST#.
• WARM_RST# — This is an asynchronous input pin which resets the entire chip
with the exception of ‘sticky’ bits in the PMMR registers. All reset straps are
sampled at the rising edge of WARM_RST#.
• PCI Express Hot Reset — When operating as an endpoint and the Hot Reset
sequence is received in the TS1 ordered set, the entire chip is reset with the
exception of the PCI Express physical layer and ‘sticky’ bits in the PMMR registers.
This reset is not applicable when the PCI Express interface is disabled. A subset of
straps are sampled as described in Section 17.5, “Reset Strapping Options”
• PCI Express Loopback — When operating as an endpoint and the Loopback
sequence is received in the TS1 ordered set, the entire chip is reset with the
exception of the PCI Express physical layer and “sticky” bits in the PMMR registers.
This reset is not applicable when the PCI Express interface is disabled. A subset of
straps are sampled as described in Section 17.5, “Reset Strapping Options”
• PCI Express Disable Link — When operating as an endpoint and the Disable Link
sequence is received in the TS1 ordered set, the entire chip is reset with the
exception of the PCI Express physical layer and “sticky” bits in the PMMR registers.
This reset is not applicable when the PCI Express interface is disabled. A subset of
straps are sampled as described in Section 17.5, “Reset Strapping Options”
• PCI Express Link Down — When operating as an endpoint and the PCI Express
Link transitions to the link down state, the entire chip, including the PCI Express
physically layer, is reset with the exception of “sticky” bits in the PMMR registers.
This reset is not applicable when the PCI Express interface is disabled. A subset of
straps are sampled as described in Section 17.5, “Reset Strapping Options”