Intel CONTROLLERS 413808 - Manual (Page 358)

Intel
®
413808 and 413812—Address Translation Unit (PCI Express)
Intel ® 413808 and 413812 I/O Controllers in TPER Mode
Developer’s Manual October 2007
358 Order Number: 317805-001US
3.17.73 PCI Express Correctable Error Status - ERRCOR_STS
The Correctable Error Status register reports error status of individual correctable error
sources on a PCI Express device. When an individual error status bit is set to “1” it
indicates that a particular error occurred; software may clear an error status by writing
a 1 to the respective bit
Note: All bits in this register are sticky through reset.
Table 213. PCI Express Correctable Error Status - ERRCOR_STS
Bit Default Description
31:14 0 Reserved - Software must write 0 to these bits.
13 0 Advisory Non-Fatal Error Status
12 0 Replay Timer Timeout Status: Set whenever a replay timer timeout occurs.
11:9 0 Reserved - Software must write 0 to these bits.
8 0 REPLAY_NUM Rollover Status: Set whenever the replay number rolls over from 11 to 00.
7 0 Bad DLLP Status: Sets this bit on CRC errors on DLLP.
6 0 Bad TLP Status: Sets this bit on CRC errors or sequence number out of range on TLP.
5:1 0 Reserved - Software must write 0 to these bits.
0 0 Receiver Error Status: Set whenever the physical layer detects a receiver error.
PCI
IOP
Attributes
Attributes
28 24 20 16 12 8 4 0 31
rz
rz
rz
rz
rz
rz
rz
rz
rz
rz
rz
rz
rz
rz
rz
rz
rz
rz
rz
rz
rz
rz
rz
rz
rz
rz
rz
rz
rz
rz
rz
rz
rz
rz
rz
rz
rc
rc
rc
rc
rz
rz
rz
rz
rz
rz
rc
rc
rc
rc
rc
rc
rz
rz
rz
rz
rz
rz
rz
rz
rz
rz
rc
rc
S S S S S S
Attribute Legend:
RZ = Reserved Zero
PR = Preserved
RS = Read/Set
RW = Read/Write
RC = Read Clear
RO = Read Only
NA = Not Accessible
Internal Bus Address Offset
+110H