Sram dma unit (sdma)—intel, Bit default description, Intel – Intel CONTROLLERS 413808 User Manual

Page 447: Intel xscale

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Intel

®

413808 and 413812 I/O Controllers in TPER Mode

October 2007

Developer’s Manual

Order Number: 317805-001US

447

SRAM DMA Unit (SDMA)—Intel

®

413808 and 413812

5.4.1

LocalToHost Destination Lower Address Register - L2H_DLAR

The LocalToHost Destination Lower Address Registers (L2H_DLAR) represent the lower

32-bits of the destination (host) address.

5.4.2

LocalToHost Destination Upper Address Register - L2H_DUAR

The LocalToHost Destination Upper Address Register (L2H_DUAR) represents the upper

32-bits of the destination (host) address.

Table 299. LocalToHost Destination Lower Address Register - L2H_DLAR

Bit

Default

Description

31:00

00000000H

Destination Lower Address Register (DLAR) - Read/Write

This field specifies the low-order 32 bits of the destination (host) memory address. This field is CLEARED

by a hardware or software reset.

Coprocessor

IOP

Attributes

Attributes

28

24

20

16

12

8

4

0

31

rw

na

rw

na

rw

na

rw

na

rw

na

rw

na

rw

na

rw

na

rw

na

rw

na

rw

na

rw

na

rw

na

rw

na

rw

na

rw

na

rw

na

rw

na

rw

na

rw

na

rw

na

rw

na

rw

na

rw

na

rw

na

rw

na

rw

na

rw

na

rw

na

rw

na

rw

na

rw

na

Intel XScale

®

Microarchitecture internal bus address offset

18204H

Attribute Legend:

RV = Reserved

PR = Preserved

RS = Read/Set

RW = Read/Write

RC = Read Clear

RO = Read Only

NA = Not Accessible

Table 300. LocalToHost Destination Upper Address Register - L2H_DUAR

Bit

Default

Description

31:00

00000000H

Destination Upper Address Register (DUAR) - Read/Write

This field specifies the upper-order 32 bits of the destination (host) memory address. This field is

CLEARED by a hardware or software reset.

Coprocessor

IOP

Attributes

Attributes

28

24

20

16

12

8

4

0

31

rw

na

rw

na

rw

na

rw

na

rw

na

rw

na

rw

na

rw

na

rw

na

rw

na

rw

na

rw

na

rw

na

rw

na

rw

na

rw

na

rw

na

rw

na

rw

na

rw

na

rw

na

rw

na

rw

na

rw

na

rw

na

rw

na

rw

na

rw

na

rw

na

rw

na

rw

na

rw

na

Intel XScale

®

Microarchitecture internal bus address offset

18208H

Attribute Legend:

RV = Reserved

PR = Preserved

RS = Read/Set

RW = Read/Write

RC = Read Clear

RO = Read Only

NA = Not Accessible

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