Intel CONTROLLERS 413808 - Manual (Page 5)

Intel ® 413808 and 413812 I/O Controllers in TPER Mode
October 2007 Developer’s Manual
Order Number: 317805-001US 5
Contents—Intel
®
413808 and 413812
2.7.5.1 Master Aborts for Outbound Read or Write Request ..................... 109
2.7.5.2 Inbound Read Completion or Inbound Configuration Write Completion
Message110
2.7.5.3 Master-Aborts Signaled by the ATU as a Target........................... 110
2.7.5.3.1 Uncorrectable Address Errors ...........................................110
2.7.5.3.2 Internal Bus Master-Abort ................................................. 110
2.7.6 Target Aborts on the PCI Interface.......................................................... 111
2.7.6.1 Target Aborts for Outbound Read Request or Outbound Write Request.
111
2.7.6.2 Inbound Read Completion or Inbound Configuration Write Completion
Message112
2.7.6.3 Target-Aborts Signaled by the ATU as a Target........................... 112
2.7.6.3.1 Internal Bus Master Abort..................................................112
2.7.6.3.2 Internal Bus Target Abort ..................................................112
2.7.6.3.3 Inbound EROM Memory Write .......................................... 112
2.7.7 Corrupted or Unexpected Split Completions ............................................. 113
2.7.7.1 Completer Address.................................................................. 113
2.7.7.2 Completer Attributes ............................................................... 113
2.7.8 SERR# Assertion and Detection.............................................................. 114
2.7.9 Internal Bus Error Conditions ................................................................. 115
2.7.9.1 Master Abort on the Internal Bus .............................................. 115
2.7.9.1.1 Inbound Write Request...................................................... 115
2.7.9.1.2 Inbound Read Request ..................................................... 116
2.7.9.2 Target Abort on the Internal Bus............................................... 117
2.7.9.2.1 Conventional Mode ........................................................... 117
2.7.9.2.2 PCI-X Mode .......................................................................117
2.7.9.3 Parity Error on the Internal Bus ................................................ 118
2.7.9.3.1 Conventional Mode ........................................................... 118
2.7.9.3.2 PCI-X Mode .......................................................................118
2.7.10 ATU Error Summary ............................................................................. 119
2.8 Message-Signaled Interrupts............................................................................. 125
2.9 Internal Interrupts .......................................................................................... 126
2.10 Vital Product Data ........................................................................................... 127
2.10.1 Configuring Vital Product Data Operation................................................. 127
2.10.2 Accessing Vital Product Data.................................................................. 128
2.10.2.1 Reading Vital Product Data....................................................... 128
2.10.2.2 Writing Vital Product Data........................................................ 129
2.11 Multi-Function Support..................................................................................... 130
2.11.1 PCI-X Interface Control Parameters ........................................................ 130
2.11.2 PCI-X Interface Status Reporting............................................................ 131
2.12 Central Resource Functionality .......................................................................... 132
2.12.1 Multi-Function Support.......................................................................... 132
2.12.2 Outbound Transactions ......................................................................... 132
2.12.3 PCI Reset ( P_RSTOUT# )...................................................................... 132
2.12.4 PCI Clock Outputs ( P_CLKOUT , P_CLKO[3:0] ) ...................................... 132
2.12.5 External Clock Driver ( CR_FREQ[1:0] ) .................................................. 133
2.12.6 Bus Mode and Frequency Initialization..................................................... 134
2.13 Embedded Bridge Functionality ......................................................................... 138
2.14 Register Definitions ......................................................................................... 139
2.14.1 PCI Configuration Registers ................................................................... 139
2.14.2 Internal Bus Registers........................................................................... 143
2.14.3 ATU Vendor ID Register - ATUVID .......................................................... 147
2.14.4 ATU Device ID Register - ATUDID........................................................... 147
2.14.5 ATU Command Register - ATUCMD ......................................................... 148
2.14.6 ATU Status Register - ATUSR................................................................. 149
2.14.7 ATU Revision ID Register - ATURID......................................................... 151