Intel CONTROLLERS 413808 - Manual (Page 117)

Intel ® 413808 and 413812 I/O Controllers in TPER Mode
October 2007 Developer’s Manual
Order Number: 317805-001US 117
Address Translation Unit (PCI-X)—Intel
®
413808 and 413812
2.7.9.2 Target Abort on the Internal Bus
Target Aborts can be seen by the internal bus requester interface during inbound read
operations to the memory controller. During inbound read operations, the memory
controller is capable of signalling a target abort when a multi-bit, unrecoverable ECC
error is encountered. This can occur during any read operation.
Note target aborts are signalled on a Qword basis. When either Dword of a Qword
target aborts, both are considered to have target aborted.
The Memory Controller is responsible for creating an interrupt to the Intel XScale
®
processor for any multi-bit ECC errors.
2.7.9.2.1 Conventional Mode
When operating in the Conventional PCI mode, when the data word which was target
aborted on the internal bus is actually requested and delivered on the PCI Bus, and the
ATU ECC Target Abort Enable bit is set in the ATUIMR, a target abort is returned to the
PCI initiator on that data word. When the ATU ECC Target Abort Enable bit is cleared in
the ATUIMR, a disconnect with data is returned to the PCI initiator during the data word
that was target aborted on the internal bus. In both cases, the IRQ is flushed after the
completion cycle is performed on the PCI bus
The following additional actions with the given constraints are performed by the ATU
when a target abort is signaled by the PCI target interface during an inbound read
transaction:
• Set the Target Abort (target) bit (bit 11) in the ATUSR.
• When the ATU PCI Target Abort (target) Interrupt Mask bit in the ATUIMR is clear,
set the PCI Target Abort (target) bit in the ATUISR. When set, no action.
2.7.9.2.2 PCI-X Mode
When operating in the PCI-X mode, a Target-Abort of an inbound read transaction (split
read request) on the Internal Bus results in the following actions.
• The ATU initiates a Split Completion Error Message (with message class=2h -
completer error and message index=81h - 4138xx internal bus target abort) on the
PCI bus.
• When the Initiated Split Completion Error Message Interrupt Mask in the ATUIMR is
clear, set the Initiated Split Completion Error Message bit in the ATUISR. When set,
no action.
Note: This split completion error message includes a device specific message index. The error
handler would need to have knowledge of the device specific error messages of the
4138xx in order to fully diagnose the problem.