21 msi next item pointer register - msi_next_ptr, 286 msi next item pointer register - msi_next_ptr, Section 4.7.21, “msi next – Intel CONTROLLERS 413808 User Manual
Page 430: Item pointer register - msi_next_ptr, Intel, Bit default description
Intel
®
413808 and 413812—Messaging Unit
Intel
®
413808 and 413812 I/O Controllers in TPER Mode
Developer’s Manual
October 2007
430
Order Number: 317805-001US
4.7.21
MSI Next Item Pointer Register - MSI_Next_Ptr
The Next Item Pointer Register bits adhere to the definitions in the PCI Local Bus
Specification, Revision 2.2. This register describes the location of the next item in the
function capability list. For the 4138xx that is the PCI-X capability header at offset E0H.
Note:
Refer to the Peripheral Registers Chapter for the default internal bus address. This
register is part of the configuration space of the Address Translation Unit that is setup
as an endpoint.
Table 286. MSI Next Item Pointer Register - MSI_Next_Ptr
Bit
Default
Description
07:00
D0H
MSI_Next_ Pointer
- This field provides an offset into the function configuration space pointing to the
next item in the function capability list
PCI
IOP
Attributes
Attributes
7
4
0
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
Attribute Legend:
RV = Reserved
PR = Preserved
RS = Read/Set
RW = Read/Write
RC = Read Clear
RO = Read Only
NA = Not Accessible
PCI Configuration Offset
A1H
Internal Bus Address Offset
0A1H