Intel CONTROLLERS 413808 - Manual (Page 819)

Intel ® 413808 and 413812 I/O Controllers in TPER Mode
October 2007 Developer’s Manual
Order Number: 317805-001US 819
Peripheral Registers—Intel ® 413808 and 413812
19.7 PCI Configuration Space
The PCI Configuration space of the 4138xx varies depending on the DFSEL,
INTERFACE_SEL_PCIX#, and CONTROLLER_ONLY# straps. The PCI Functions that are
visible in via configuration transactions are details in Table 547, “Intel® 413808 and
413812 I/O Controllers in TPER Mode PCI Function Visibility” .
Configurations cycles that target 4138xx are translated into memory cycles on the
internal bus and access the PCI Attributes section of the PMMR region.
19.8 Coprocessor Register Space
The CCR address space is assigned to support the integrated peripherals on the 4138xx
that require low latency register access. Table 548 shows all of the 4138xx integrated
coprocessor registers and assigned coprocessor space. The ARM Architecture Reference
Manual provides for a total of 16 coprocessors each of which can contain up to 256
32 bit registers. For completeness, the coprocessor space reserved by the ARM
Architecture Reference Manual is shown.
Note: All accesses to CP6 unimplemented coprocessor registers complete and return 0s when
read and show as “undefined”. The same rule applies to unimplemented 4138xx.
co-processors.
Table 547. Intel
®
413808 and 413812 I/O Controllers in TPER Mode PCI Function
Visibility
PCI Function Number
DFSEL 0 1 2 3 4 5 6 7
000 ATUX a ; ATUE b ;
a. ATUX is visible in function 0 when the INTERFACE_SEL_PCIX# strap is sampled as 0 and CONTROLLER_ONLY#
= 1.
b. ATUE is visible in function 0 when the INTERFACE_SEL_PCIX# strap is sampled as 1 and CONTROLLER_ONLY#
= 1.
Reserved
001
through
111
ATUX; ATUE Reserved Reserved
Table 548. Coprocessor Registers Assigned to Integrated Peripherals
Integrated Peripheral Coprocessor
Inter-Processor Communication Unit CP6
Interrupt Control Unit CP6
Programmable Timers CP6
Bus Interface Unit CP7
Core Performance Monitoring Unit CP14
System Control a
a. Reserved by the
ARM Architecture Reference Manual
.
CP15