Intel CONTROLLERS 413808 - Manual (Page 321)

Intel ® 413808 and 413812 I/O Controllers in TPER Mode
October 2007 Developer’s Manual
Order Number: 317805-001US 321
Address Translation Unit (PCI Express)—Intel
®
413808 and 413812
3.17.32 Inbound ATU Translate Value Register 1 - IATVR1
The Inbound ATU Translate Value Register 1 (IATVR1) in conjunction with the “Inbound
ATU Upper Translate Value Register 1 - IAUTVR1” on page 321 contain bits 35 to 12 of
the internal bus address used to convert PCI Express Link addresses. The converted
address is driven on the internal bus as a result of the Inbound ATU address
translation.
3.17.33 Inbound ATU Upper Translate Value Register 1 - IAUTVR1
The Inbound ATU Upper Translate Value Register 1 (IAUTVR1) in conjunction with the
“Inbound ATU Translate Value Register 1 - IATVR1” on page 321 contain bits 35 to12 of
the internal bus address used to convert PCI Express Link addresses. The converted
address is driven on the internal bus as a result of the inbound ATU address translation.
Table 172. Inbound ATU Translate Value Register 1 - IATVR1
Bit Default Description
31:12 00000H
Inbound ATU Translation Value 1 - Bits 31 to 12 of the internal bus address used to convert PCI address
to internal bus addresses. This value must be naturally aligned with the IABAR1 register’s programmed
value (see
Section 3.17.15, “Determining Block Sizes for Base Address Registers” on
page 306
).
11:01 000H Reserved
00 0
Big Endian Byte Swap enable - When set the ATU performs a byte swap on all PCI read/write
transactions through BAR1. When clear, no swap is performed. Refer to Section 3.4, “Big Endian Byte
Swapping” on page 255 for more details.
PCI
IOP
Attributes
Attributes
28 24 20 16 12 8 4 0 31
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rw
rw
Attribute Legend:
RV = Reserved
PR = Preserved
RS = Read/Set
RW = Read/Write
RC = Read Clear
RO = Read Only
NA = Not Accessible
Internal Bus Address Offset
+050H
Table 173. Inbound ATU Upper Translate Value Register 1 - IAUTVR1
Bit Default Description
31:04 000 0000H Reserved
3:0 0H
Inbound Upper ATU Translation Value 1 - This value represents bits 35 to 32 of the internal bus address
used to convert the PCI address to internal bus addresses.
PCI
IOP
Attributes
Attributes
28 24 20 16 12 8 4 0 31
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rw
rw
rw
rw
rw
rw
rw
rw
Attribute Legend:
RV = Reserved
PR = Preserved
RS = Read/Set
RW = Read/Write
RC = Read Clear
RO = Read Only
NA = Not Accessible
Internal Bus Address Offset
+054H