Intel CONTROLLERS 413808 - Manual (Page 810)

Intel ® 413808 and 413812—Peripheral Registers
Intel ® 413808 and 413812 I/O Controllers in TPER Mode
Developer’s Manual October 2007
810 Order Number: 317805-001US
19.6.2.1 Address Translation Unit (PCI-X)
A subset of the ATU registers are accessible through both inbound PCI configuration
cycles and the 4138xx core CPU (Register offsets 000H through 0FFH). The balance of
the registers are accessible only via the internal bus.
The Internal Bus Address Offset to PMMRBAR of any ATU Register can be derived by
adding the 4 KB address aligned Internal Bus Memory Mapped Register Range Offset
( Table 543, “Intel® 413808 and 413812 I/O Controllers ATUX Configuration Space
Base Address Offset” on page 810 ) to the Register Offset ( Table 544, “Address
Translation Unit Registers — ATUX” on page 811 )
For example, when INTERFACE_SEL_PCIX# and CONTROLLER_ONLY# are
bothasserted, the offset to PMMRBAR of the ATU Command Register would be
(4 C000H+004H) or 4 C004H.
Note: The 4 KB Address Aligned Range Offset can be different depending on two configuration
straps as described in Table 543 .
T
Table 543. Intel
®
413808 and 413812 I/O Controllers ATUX Configuration Space Base
Address Offset
CONTROLLER_ONLY# INTERFACE_SEL_PCIX# ATUX Base Address Offset (Relative to PMMRBAR)
PCI Attributes
Deasserted Asserted +4 0000H
Asserted Deasserted +4 4000H
Asserted Asserted +4 4000H
Deasserted Deasserted +4 5000H
Local Attributes
Deasserted Asserted +4 8000H
Asserted Deasserted +4 C000H
Asserted Asserted +4 C000H
Deasserted Deasserted +4 D000H