Intel CONTROLLERS 413808 - Manual (Page 90)

Intel
®
413808 and 413812—Address Translation Unit (PCI-X)
Intel ® 413808 and 413812 I/O Controllers in TPER Mode
Developer’s Manual October 2007
90 Order Number: 317805-001US
2.6.3.1 Transaction Ordering Summary
Table 15 and Table 16 , define transaction ordering in relation to token assignment of
the priority mechanism (this is discussed in Section 2.6.3 ). These tables are read as
follows:
1. As the transaction enters the head of the respective queue, the question in column
2 is asked.
2. When all the answers in column 3 for a given transaction type assigns a token to
the transaction at the head of the queue, a token is assigned. Otherwise, no token
is assigned signifying that transaction ordering must first be satisfied. Any
transaction with a token may be initiated on the bus.
Table 15. Inbound Transaction Ordering Summary
Transaction at
Head of Queue
Question Answer Action
Inbound Write in
IWQ
Is there an Inbound Write Request with
an earlier time stamp?
Yes
Do Not Assign Token
Allow previous Transaction to Complete
No Assign Token
Inbound Read
Request in ITQ
Is there an Inbound Write with an
earlier time stamp?
Yes
Do Not Assign Token
Allow previous Transaction to Complete
No Assign Token
Is there an Inbound Read Request with
an earlier time stamp?
Yes
Do Not Assign Token
Allow previous Transaction to Complete
No Assign Token
Is there an Inbound Configuration Write
Request with an earlier time stamp?
Yes
Do Not Assign Token
Allow previous Transaction to Complete
No Assign Token
Inbound
Configuration
Write Request in
IDWQ
Is there an Inbound Write with an
earlier time stamp?
Yes
Do Not Assign Token
Allow previous Transaction to Complete
No Assign Token
Is there an Inbound Read Request with
an earlier time stamp?
Yes
Do Not Assign Token
Allow previous Transaction to Complete
No Assign Token
Outbound Read
Completion in
ORQ
Is there an Inbound Write with an
earlier time stamp?
Yes
Do Not Assign Token
Allow previous Transaction to Complete
No Assign Token